This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/MSP430F1611: Tx Buffer empty - not done

Part Number: MSP430F1611

Tool/software: Code Composer Studio

I am using the transmit buffer empty flag in an ISR to signal when the transfer is done.  This is in a system that is using 485 two wire so an additional IO is used to set the direction of the 485 driver chip.  I find that if and do not insert a delay after detecting that the transmit buffer is empty the direction control gets set to receive before the last bit is actually done.  In fact if I apply any UART control bits to turn the serial communications around to receive inside the msp such as putting the Uart in reset with SWRST or change the ME bits the data does not complete.  I find I have to do a for loop for at least 10 counts before doing anything to turn around to the receive condition.  The msp is running at 7.3MHz and the baud rate is 230400.

Is this typical for msp430, or is there something else I should be looking at inside the UART state machine to guaranty that all the data has cleared the port including the stop bit?  (8N1). 

  • As stated in the User's Guide, UTXIFGx is set when UxTXBUF is ready for new data but does not indicate that the previous byte has finished being sent out of the MCU. You cannot therefore rely on the UTXIFGx bit to determine when to switch direction control. You can instead try to poll the TXEPT bit to tell if the UART is not currently transmitting data or if data is waiting in UxTXBUF.

    Regards,
    Ryan
  • I am polling the TXEPT bit.  Which the user manual indicates that both the buffer and the shift register should be done.  It is after this that I turn the UART around for Rx operation.  If I do not have a delay after TXEPT is 1 then the receiving end does not get all the data.

  • My mistake, in this case you've already implemented the best solution by incorporating an additional delay.

    Regards,
    Ryan

**Attention** This is a public forum