Hello Team,
Posting on behalf of my Customer:
We are using the USI (as a timer resource, not SPI/I2C) on a MSP430G2452 and clocking from a source asynchronous(ACLK) to the CPU clock. Are there any known issues with the clock divider going into latch-up if the USIIFG signal and the input to the clock divider are asynchronous and happen to line up just perfect? We are getting a dead USI and can’t really trace it to much else. Any input you have would be appreciated.
(Refer to Figure 14-1 in Family Users Guide) We are setting USIIFG in software to stop the clock (ACLK) and once in a blue moon (probably 1 in a billion) it takes a complete power-down to recover.