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MSP430FR5994: Upsampling with LEA

Alexey Bagaev
Genius 5435 points
Part Number: MSP430FR5994

Hi TI,

I need to capture at sample rate of 32kHz, do 2-stage 4x decimation with 6-th order filtering (probably FIR), compression/decompression, and finally 4x upsampling with 6-th order filtering and sending data to DAC in real-time. Is MSP430FR5994 with LEA powerful enough for such real-time process provided that compression/decompression is not a computation dominant in this process? And what upsampling technique I need to choose to fit in restricted MSP resources (clock speed, etc.).

Thanks,

Alexey

  • 0
    TI__Genius 14875 points
    Alexey,
    We are working on this for you. We will respond shortly.
  • 0 in reply to Cameron LaFollette
    TI__Intellectual 1930 points

    Hi Alexey,

    While the MSP DSP library doesn't include FIR filters with decimation and upsampling you can create your own implementation using the FIR function along with the interleave and deinterleave functions. An example implementation processing samples in blocks of 256 is shown in the steps below. I've included cycle estimates which are taken from the table on page 20 of  Benchmarking the Signal Processing Capabilities of the Low-Energy Accelerator on MSP430.

    1. 6th order low-pass FIR filter to remove high frequency components before decimating
      1. msp_fir_q15()
      2. 17+256/2*(12+4*6/2) = 3089 cycles

    2. Decimation using the deinterleave function to extract every 4th sample
      1. msp_deinterleave_q15()
      2. 16+3*64/2 = 112 cycles
    3. Compession/decompression
    4. Zero initialize destination array
      1. msp_fill_q15()
      2. 14+3*256/2 = 398 cycles

    5. Upsample using the interleave function to insert every 4th sample
      1. msp_interleave_q15()
      2. 17+5*64/2 = 177 cycles
    6. 6th order low-pass FIR filter to smooth upsampled signal
      1. msp_fir_q15()
      2. 17+256/2*(12+4*6/2) = 3089 cycles

    The total cycle count is 6865, not including API overhead which we can be generous and round up to 8000 clock cycles for 256 samples. At 8 MHz clock speed that's 1 ms per 256 sample block, sampling at 32KHz would be 125 blocks giving a total of 125 ms or 12.5% of available clock cycles.

    Regards,

    Brent Peterson

  • 0 in reply to Brent Peterson
    Genius 5435 points

    Thank you, Brent for your research.

    I've also done some on actual device with spectrogram. The good news, you've pointed out to LEA hardware functions which do fast interleaving/deinterleaving. The bad news, the FIR filter cannot do 6-th order filtering with 6 taps. It needs about 255 taps to do this big roll-off. So, the processing buffer should also be extended to 512 sample block at least. That's why I asked for this.

    But thank you for detailed explanation how to do this.

    Regards,

    Alexey

  • 0 in reply to Alexey Bagaev
    Genius 5435 points

    Looks, like I found good balance: FIR Hamming Window method with 63 taps.
    Consider this thread closed and answered.

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