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MSP430F5329: Interrupt generated by unlocked frequency loop

Part Number: MSP430F5329

Team,

my customer wants to generate an interrupt from the FLL. They found some confusing information which is contradictory:

The question is about the 1Ch value (Reserved) on the SYSRSTIV Register.

  • The msp430f5329.h file mentions this value in the definition of the SYSRSTIV (see attached screenshot). It is defined as SYSRSTIV_FLLUL 0x1C.
  • The datasheet says this values is "reserved". The datasheet history says: "Table 11, Changed SYSRSTIV interrupt event at 1Ch to Reserved."

Can you support to clarify the situation?
Is it possible to have an interrupt generated by an Unlocked Frequency Loop on the MSP430F5329?

 

Thanks!

 


  • Hi,

    After reviewing the datasheet and user's guide for the Unified Clock System (UCS) module, the MSP430F5329 does not have FLL unlock detection. It looks like the header file was not updated to reflect the change in the datasheet either. I'll double check with our systems team to confirm this.

    To have FLL unlock detection capability the device must have a Clock System (CS) module. This would include devices like the MSP430FR4xx and MSP430FR2xx family of devices.

    Best regards,
    Caleb Overbay
  • Caleb,

    were you able to double check?

    The reason my customer asked was that they check for the origin of resets in the  SYSRSTIV register.
    They want to make sure the FLL reset option is not possible on this device and if after a reset the SYSRSTIV can have a value greater than SYSRSTIV_WDTKEY for any other reason (even value not mentioned in the datasheet).

    Thanks!

  • Hi,

    I haven't heard a response yet. I'll ping them again and let you know what I hear. Thanks for your patience!

    Best regards,
    Caleb Overbay

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