This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430F5438: Logic levels for USCI I2C inputs

Part Number: MSP430F5438

Hi champs,

we cannot find logic level definitions for SDA line in DS:

- what are  Vin-low_max and Vin-high_min thresholds  when using I2C bus

- what is RDS_on of open drain FET

Customer need detaisl to calculate worst case scenario for his use case.

  • Hi DJ-NG,

    I2C input logic levels are the same as Schmitt-Trigger Inputs for GPIOs, the thresholds are provided in Section 5.7 of the Datasheet. Internal FET specifications are not provided by TI.

    Regards,
    Ryan
  • Hi Ryan,

    As per section 5.7 it is not clear.

    VIT+ = 1.5V to 2.10 for 3V Supply
    VIT- = 0.75V to 1.65V for 3V Supply.

    Assume my input is 1.5V level in this case MSP430 what will be consider high or low logic level?

    Thanks
    Sathiyan
  • Schmitt-trigger inputs have hysteresis.

    When the signal is in the high state, you need to a level of 0.75 V to switch to the low state. (The actual threshold might be anywhere between 0.75 V and 1.65 V.)
    When the signal is in the low state, you need to a level of 2.10 V to switch to the high state. (The actual threshold might be anywhere between 1.50 V and 2.10 V.)
    So for a voltage between 0.75 V and 2.10 V, the input might stay in the previous state.

**Attention** This is a public forum