Part Number: MSP430F5659
I have configured DAC0 to P7.6, output to 400 mV.
P6.6 (which could be configured as DAC0 too) is configured as digital output, not as DAC0.
When rising P6.6, I see DAC0 falling for about 15 us.
Any solution for this? Thank you.
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In reply to Wei.Jetim Zhao:
Increasing the current of the DAC's input buffer does not help. Increasing the current of the output buffer helps reducing the glitch duration, but not its amplitude.
No news yet?
In reply to Gabriel Barbat:
In reply to Ryan Brown1:
DAC12OPS is set.
DAC12AMPx is what I changed before.
Now I tried setting PxDS on P6.6 only, on P7.6 only and on both. It didn't help in any case.
I'm not sure what you mean with "pad logic".
Got it. Please let me know if you have more information.
I actually already have a 100 pF capacitor. I didn't evalute the behavior either without the capacitor or with a bigger capacitor. Increasing the capacitor could increase the settling time. I need it to be less than ~50us.
Could you suggest a capacitor value that would help?
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