MSP430F6736A: RTC_C not ticking over on battery backup

Hi Ryan

Thanks for your response.

Just some initial points:

i'm using a F6736A not a F6779;
i'm not going into LPM3.5 (or any mode) i'm simply looking at the situation where main power has gone & the RTC_C is now being powered by the battery (when main power is ON, AUXCC3 is powering the RTC_C).

So having said that...i looked at the 06.c & decided to try a situation whereby the RTC_C is powered EXCLUSIVELY by the battery.
To do that, in my setup lines (which are the 1st few lines in main),  i commented out my line AUX3CHCTL = AUXCHKEY | AUXCHV_1 | AUXCHC_1 | AUXCHEN;
and replaced it with just AUX3CHCTL = AUXCHKEY;  which is really resetting it to what it was when control entered my main().

On the hardware side i have the following:

My scope probe is on XTAL1 IN (pin24).
Bench PSU to the battery is set at 3.3V.
Ammeter on +ve wire sitting between the bench PSU and the battery holder.

So the results:

With the MCU running off normal main power, the backup mem+RTC_C are running (current drawn on bench PSU 1.2uA & scope  shows the crystal waveform).
I check that the RTC_C is running via a comms program i wrote that communicates with my firmware via eUSCI and i see that RTC_C is ticking over correctly.
The waveform DOESNT change in any manner when power is removed.
I wait 30secs and restore main power & check RTC_C again....it has only progressed the 2 secs or so for my to disconnect main, reconnect main, & click my 'Get Time' button....ie when main power resumes, the RTC_C resumes with the SAME values it LAST had when main power was removed.

This tells me that during the time main power was removed the RTC_C did NOT lose its contents but it also did NOT increment the time!

The ONLY discernible difference between this test and the normal situation whereby RTC_C is powered by AUXCC3 is in the following:

When AUXCC3 is DISabled (this test above):

The 32K crystal waveform does NOT move when main power is removed and restored.
And the power drawn remains constant at 1.2uA.

When AUXCC3 is ENabled (the normal situation):

The 32K waveform dips momentarily in the crossover from AUXVCC3 to battery.
The power drawn under main power is 0A and when main is removed, the power drawn goes to 1.2uA.

So...next step?

Hi Ryan

The waveform SHAPE (nice sine curve) via battery or via AuxVcc3 is the same..the magnitude IS slightly different.

i set the bench PSU at 3.3V

Given the scenario where AuxVcc3 is DISsabled:

The waveform max/min is 2.60V &  2.39V, current drawn from PSU is 1.0uA REGARDLESS of whether main power is applied or not.

And When the AuxVcc3 is ENabled:

With main power powering the board, the waveform max/min becomes 2.66V & 2.45V, current drawn is 0uA.

When main power is removed the waveform max/min is 2.60V &  2.39V, current drawn is 1.0uA

Code...

AUX3CHCTL = AUXCHKEY | AUXCHV_1 | AUXCHC_1 | AUXCHEN;  // Charger for AUX3...Vcc, 5K resistor, enable

RTCCTL0_H = RTCKEY_H;                      // Unlock RTC_C module

RTCCTL0_L |= RTCRDYIE;   //  read ready interrupt (every sec)

RTCCTL1 = 0;

RTCCTL1 = 0x00 | RTCHOLD | RTCMODE;  // RTC enable binary mode ~RTCBCD, RTC hold, calendar mode

RTCCTL1 &= ~RTCHOLD;      // Start RTC calendar mode

RTCCTL0_H = 0;              // Lock RTC_C module

there is no code i can present to demonstrate that the RTC is not ticking over..it is an observation (which is how i discovered this unexpected problem).

Read the clock, Remove power, Wait a minute, Read the clock.

For schematics: 

cheers

moshe

What is the CPU frequency and has PMMCOREV been stepped up correctly?  Have you considered testing with a dedicated power supply at AUXVCC3 instead of a battery? Humor me by unlocking the PMM registers (PMMCTL0_H = PMMPW_H;) before modifying AUX3CHCTL and confirm through the debugger that all bits are set correctly afterwards.  I think I have everything necessary to try and re-create this issue.

Regards,
Ryan

Hi Ryan

Q: What is the CPU frequency?
A: I believe its 16MHz or is it 8MHz?

This is how it is set up (XT1 is the FLLREF CLK of 32768).

UCSCTL0 = 0; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // the permissible range for this is 6MHz-23.7MHz see fig10 datasheet
UCSCTL2 = FLLD_1 | 255; //sets FLLN to 255 so (N+1)=256, FLLD = 1 so D = 2....
UCSCTL3 = SELREF_0 | FLLREFDIV_0; //its the default
UCSCTL4 = SELM__DCOCLK | SELS__DCOCLK | SELA__XT1CLK; //MCLK & SMCLK come from DCOCLKDIV (8MHz), 32KHz ACLK
UCSCTL5 |= DIVS__1; // this effectevly sets UCSCTL5 to 0 which means no division of any of the ACLK, MCLK, SMCLK clks

According to the user guide fDCOCLKDIV = MCLK = (N+1)x32768 = (255+1)x32768 which makes it 8MHz
fDCOCLK = fDCOCLKDIV*D = 16MHz

I noticed that PMMCOREV was kept at the default 0 so i added this line BEFORE setting the DCO.....but it made no difference
PMMCTL0 = 0xa503; // sheesh...forgot to set it to Vcore3...see fig5-1 in datasheet

I also set this line immediately after the PMM line
AUX3CHCTL = AUXCHKEY; //DISABLE charger so only battery is used - testing for TI

Q: Have you considered testing with a dedicated power supply at AUXVCC3
A: Since i discovered the issue i have ONLY been testing with the bench PSU at AUXVCC3.

Regarding hunouring you...yes i have by adding the line to get it to coreV3
And i checked that AUX3HCTL remained set to what i wanted by executing PMMCTL0_H = 0; and checking AUX3HCTL.

So next thing to try?

cheers
Moshe

Hi Ryan
Yes, the FLL control loop is disabled before any of the above & enabled after the above (after the UCSCTL5 assignment).

My understanding is that due to the line
UCSCTL4 = SELM__DCOCLK | SELS__DCOCLK | SELA__XT1CLK;
MCLK is at fDCO which in this case is 16MHz.
(i was incorrect in saying in the previous post that MCLK is from fDCOCLKDIV)

I understand that correct transitioning is required...
and i have just implemented the code based on msp430f665x_ucs_03.c SetVCoreUp
but i dont see how the PMM function would have any bearing on what happens to the RTC when it is operating on AUXVCC3 via a bench PSU & main power is removed.

As it is...i still have the problem of RTC not ticking over on main power removal.

regards
moshe

Hi moshe,

The following code operated properly using the MSP-TS430PZ100B with a 32 kHz external crystal and load capacitors.  With JP4, JP11, and JP12 unpopulated to remove DVCC, AUXVCC1, and AUXVCC2, respectively, RTCSEC and RTCTIM0 still incremented from AUXVCC3 power.

#include <msp430.h>

void SetVcoreUp (unsigned int level);

void main(void)
{
    WDTCTL = WDTPW | WDTHOLD;               // Stop WTD

    // Setup P11.5 RTCCLK
    P9DIR |= BIT0;            // RTCCLK set out to pins
    P9SEL |=BIT0;

    SetVcoreUp (0x01);
    SetVcoreUp (0x02);

    //Enable Charger
    AUX3CHCTL = AUXCHKEY + AUXCHC_1 + AUXCHV_1 + AUXCHEN;

//    // Initialize LFXT1
    UCSCTL6 &= ~(XT1OFF);                   // Enable XT1
//    UCSCTL6 |= XCAP_3;                      // Internal load cap
    // Loop until XT1, XT2 & DCO fault flag is cleared

    __bis_SR_register(SCG0);                  // Disable the FLL control loop
    UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx
    UCSCTL1 = DCORSEL_5;                      // Select DCO range 24MHz operation
    UCSCTL2 = FLLD_1 + 487;                   // Set DCO Multiplier for 16MHz
                                              // (N + 1) * FLLRef = Fdco
                                              // (487 + 1) * 32768 = 16MHz
                                              // Set FLL Div = fDCOCLK/2
    __bic_SR_register(SCG0);                  // Enable the FLL control loop

    // Worst-case settling time for the DCO when the DCO range bits have been
    // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
    // UG for optimization.
    // 32 x 32 x 16 MHz / 32,768 Hz = 500000 = MCLK cycles for DCO to settle
    __delay_cycles(500000);

    do
    {
        UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);
        // Clear XT2,XT1,DCO fault flags
       SFRIFG1 &= ~OFIFG;                  // Clear fault flags
    } while (SFRIFG1 & OFIFG);              // Test oscillator fault flag

    // Start RTC calendar mode
    RTCCTL0_H = RTCKEY_H;                   // Unlock RTC_C module
    RTCCTL0_L |=  RTCRDYIE; //              // Enable RTC time event,
    RTCCTL1 |= RTCBCD;
     RTCCTL13 &=  ~(RTCCALF_3);  //Clear all RTCCALF bits since they may have previous RTCCALF value.
    RTCCTL13 |=  RTCCALF_1;     //512 Hz RTC output
    RTCCTL1 &= ~(RTCHOLD);  //In this case, RTCHOLD may be set with POR.  However, it does not
                            //get set in the case VDSYS goes off, but it does get set when it comes
                            //back.  Therefore, it should get reset to enable operation.
    RTCCTL0_H = 0;

    __bis_SR_register(GIE);
    while(1) __no_operation();
}

// RTC Interrupt Service Routine
#pragma vector=RTC_VECTOR
__interrupt void rtc_isr(void)
{
    switch (__even_in_range(RTCIV, 16))
    {
        case RTCIV_NONE:                    // No interrupts
            break;
        case RTCIV_RTCOFIFG:                // RTCOFIFG
            break;
        case RTCIV_RTCRDYIFG:               // RTCRDYIFG
            __no_operation();
            break;
        case RTCIV_RTCTEVIFG:               // RTCEVIFG
            __no_operation();
            break;
        case RTCIV_RTCAIFG:                 // RTCAIFG
            __no_operation();
            break;
        case RTCIV_RT0PSIFG:                // RT0PSIFG
            break;
        case RTCIV_RT1PSIFG:                // RT1PSIFG
            break;
//        case 14: break;                   // Reserved
        case 16: break;                     // Reserved
        default: break;
    }
}

void SetVcoreUp (unsigned int level)
{
  // Open PMM registers for write
  PMMCTL0_H = PMMPW_H;
  // Set SVS/SVM high side new level
  SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
  // Set SVM low side to new level
  SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
  // Wait till SVM is settled
  while ((PMMIFG & SVSMLDLYIFG) == 0);
  // Clear already set flags
  PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
  // Set VCore to new level
  PMMCTL0_L = PMMCOREV0 * level;
  // Wait till new level reached
  if ((PMMIFG & SVMLIFG))
    while ((PMMIFG & SVMLVLRIFG) == 0);
  // Set SVS/SVM low side to new level
  SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
  // Lock PMM registers for write access
  PMMCTL0_H = 0x00;
}

Regards, Ryan

Hi Dietmar

Thanks for highlighting that...but...we are not going into LPM3.5...main power simply fails so its a no power situation.
And, as its unknown that power is going to be cut-off, the program does nothing in advance.

Ergo, the SVS (or any other peripheral) is not touched in advance of the power failure & remains as is.

Hi,

it's not related to LPM3.5 even if you disable SVS in Active Mode you run into this problem.

Anyway if you do not touch SVS it's someting different. So does this behavior appear with debugger connected?

If yes can you please try to debug this and check if RTC is counting and if the oscillator fault flags are properly cleared.

Hi Dietmar

The SVS is altered as per the example project msp430f665x_ucs_03.c

And yes i do have the debugger connected.
While the MCU is running the RTC DOES tick over (both in my PCB and in the TI target board) .

And my oscillator checks are in setup in the following loop:

while (SFRIFG1 & OFIFG) // Check OFIFG fault flag
{
        UCSCTL7 &= ~(DCOFFG | XT1LFOFFG | XT2OFFG); // Clear OSC fault flags
        SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag
}

Even before any changes that Ryan suggested, the RTC was running while main power was applied.

i also have this line at the beginning of my setup 
           BAKMEM3 = SYSRSTIV;     // store the reg for the last startup.
which returns 2h which i believe is BOR.

AUXVCC3 is connected directly to the backup power supply (both PCB & target board).
And from the scope probe i do see the XT1 oscillator continuing to run when main power is removed.
And from my DMM i see the power draw to be 0.9 uA regardless of main power ON or OFF so i assume it indicates that everything associated with AUXVCC3 continues to function when main power is removed.

So it would appear that something is set on power down that puts the RTC into a HOLD state. Where should i look for that?

But i am also puzzled why Ryan's code makes the RTC continue to tick over under backup power yet my copy of Ryan's code does not....same code, same target board, same jumper settings(?), same MCU.

Hi Ryan
Yes i did that, and yes the RTC ticked over...but thats only because the MCU is still running (somewhere) as evidenced by being able to step thru the code in the while loop and in the ISR when those jumpers are removed, so it proves nothing except that one can remove J4, J11, & J12 and the chip still runs under FET power...i'm not sure how except it does.

The test should be performed with the RTC and the main power source from an external source but NOT the FET.
The RTC supplied solely from the external source so as to remove any issues with the AUXVCC3 chargers.
Then remove main power & return it a minute or more later and read the RTC registers....in THAT test and under THOSE circumstances the RTC does not tick over....(although the crystal keeps running & the registers are kept alive).

I dont think its a chip lot quality but rather a setting (or possibly even a connection) issue.

regards
Moshe

Hi Ryan
I communicate with my design board via RS232. Thats how i picked up the issue in the first place.
When power is restored, i read the RTC again and noticed the time only ticked over a few secs rather than the few minutes power was OFF.
The only reason i went to using a target board was because you said it worked on your setup.

So...given that...and communicating with my board...I have established that:
1. The 32K crystal continues to oscillate when main power is removed.
2. The contents of the RTC registers retain their values when power is removed.

It is almost as if RTCCTL1 has a RTCHOLD assignment.....is that possible?
Is there another setting that makes the RTC continue to tick over or conversely go into hibernation?
Is there a parallel set of registers that are used in the power down scenario that i must then copy (on restart) into the RTC registers that i use for reading the time?

regards
moshe

Hi moshe,

I've applied the following code to my MSP-TS430PZ100B target board and connected the MSP-FET pin 2 to VCC, pin 9 to GND, pin 12 to P1.3/TXD, and pin 14 to P1.2/RXD.  I can see RTCSEC incrementing properly, even during AUXVCC3 supply, using a terminal program @ 9600 baud (after DVCC has been re-connected).

#include <msp430.h>

void SetVcoreUp (unsigned int level);

void main(void)
{
    WDTCTL = WDTPW | WDTHOLD;               // Stop WTD

    // Setup P11.5 RTCCLK
    P9DIR |= BIT0;            // RTCCLK set out to pins
    P9SEL |=BIT0;

    // Setup P1.2 UCA0RXD, P1.3 UCA0TXD
    P1SEL |= BIT2 | BIT3;                   // Set P1.2, P1.3 to non-IO
    P1DIR |= BIT2 | BIT3;                   // Enable UCA0RXD, UCA0TXD

    SetVcoreUp (0x01);
    SetVcoreUp (0x02);

    //Enable Charger
    AUX3CHCTL = AUXCHKEY + AUXCHC_1 + AUXCHV_1 + AUXCHEN;

//    // Initialize LFXT1
    UCSCTL6 &= ~(XT1OFF);                   // Enable XT1
//    UCSCTL6 |= XCAP_3;                      // Internal load cap
    // Loop until XT1, XT2 & DCO fault flag is cleared

    __bis_SR_register(SCG0);                  // Disable the FLL control loop
    UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx
    UCSCTL1 = DCORSEL_5;                      // Select DCO range 24MHz operation
    UCSCTL2 = FLLD_1 + 487;                   // Set DCO Multiplier for 16MHz
                                              // (N + 1) * FLLRef = Fdco
                                              // (487 + 1) * 32768 = 16MHz
                                              // Set FLL Div = fDCOCLK/2
    __bic_SR_register(SCG0);                  // Enable the FLL control loop

    // Worst-case settling time for the DCO when the DCO range bits have been
    // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
    // UG for optimization.
    // 32 x 32 x 16 MHz / 32,768 Hz = 500000 = MCLK cycles for DCO to settle
    __delay_cycles(500000);

    do
    {
        UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);
        // Clear XT2,XT1,DCO fault flags
       SFRIFG1 &= ~OFIFG;                  // Clear fault flags
    } while (SFRIFG1 & OFIFG);              // Test oscillator fault flag

    // Start RTC calendar mode
    RTCCTL0_H = RTCKEY_H;                   // Unlock RTC_C module
    RTCCTL0_L |=  RTCRDYIE; //              // Enable RTC time event,
    RTCCTL1 |= RTCBCD;
     RTCCTL13 &=  ~(RTCCALF_3);  //Clear all RTCCALF bits since they may have previous RTCCALF value.
    RTCCTL13 |=  RTCCALF_1;     //512 Hz RTC output
    RTCCTL1 &= ~(RTCHOLD);  //In this case, RTCHOLD may be set with POR.  However, it does not
                            //get set in the case VDSYS goes off, but it does get set when it comes
                            //back.  Therefore, it should get reset to enable operation.
    RTCCTL0_H = 0;

    // Setup eUSCI_A0
    UCA0CTLW0 |= UCSWRST;                   // **Put state machine in reset**
    UCA0CTLW0 |= UCSSEL_1;                  // CLK = ACLK
    UCA0BRW_L = 0x03;                       // 32kHz/9600=3.41 (see User's Guide)
    UCA0BRW_H = 0x00;                       //
    UCA0MCTLW = 0x5300;                     // Modulation UCBRSx=0x53, UCBRFx=0
    UCA0CTLW0 &= ~UCSWRST;                  // **Initialize USCI state machine**
    UCA0IE |= UCRXIE;                       // Enable USCI_A0 RX interrupt

    __bis_SR_register(GIE);
    while(1) __no_operation();
}

// RTC Interrupt Service Routine
#pragma vector=RTC_VECTOR
__interrupt void rtc_isr(void)
{
    switch (__even_in_range(RTCIV, 16))
    {
        case RTCIV_NONE:                    // No interrupts
            break;
        case RTCIV_RTCOFIFG:                // RTCOFIFG
            break;
        case RTCIV_RTCRDYIFG:               // RTCRDYIFG
            __no_operation();
            break;
        case RTCIV_RTCTEVIFG:               // RTCEVIFG
            __no_operation();
            break;
        case RTCIV_RTCAIFG:                 // RTCAIFG
            __no_operation();
            break;
        case RTCIV_RT0PSIFG:                // RT0PSIFG
            break;
        case RTCIV_RT1PSIFG:                // RT1PSIFG
            break;
//        case 14: break;                   // Reserved
        case 16: break;                     // Reserved
        default: break;
    }
}

// USCI_A0 interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_A0_VECTOR))) USCI_A0_ISR (void)
#else
#error Compiler not supported!
#endif
{
    switch (__even_in_range(UCA0IV, 4))
    {
        case USCI_NONE: break;              // No interrupt
        case USCI_UART_UCRXIFG:             // RXIFG
            while (!(UCA0IFG & UCTXIFG)) ;  // USCI_A0 TX buffer ready?
            UCA0TXBUF = ((RTCSEC>>4)&0x0F) + 48;    // RTCSEC high byte
            while (!(UCA0IFG & UCTXIFG)) ;  // USCI_A0 TX buffer ready?
            UCA0TXBUF = (RTCSEC&0x0F)+48;   // RTCSEC low byte
            while (!(UCA0IFG & UCTXIFG)) ;  // USCI_A0 TX buffer ready?
            UCA0TXBUF = 10;
            while (!(UCA0IFG & UCTXIFG)) ;  // USCI_A0 TX buffer ready?
            UCA0TXBUF = 13;
            break;
        case USCI_UART_UCTXIFG: break;      // TXIFG
        case USCI_UART_UCSTTIFG: break;     // TTIFG
        case USCI_UART_UCTXCPTIFG: break;   // TXCPTIFG
        default: break;
    }
}

void SetVcoreUp (unsigned int level)
{
  // Open PMM registers for write
  PMMCTL0_H = PMMPW_H;
  // Set SVS/SVM high side new level
  SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
  // Set SVM low side to new level
  SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
  // Wait till SVM is settled
  while ((PMMIFG & SVSMLDLYIFG) == 0);
  // Clear already set flags
  PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
  // Set VCore to new level
  PMMCTL0_L = PMMCOREV0 * level;
  // Wait till new level reached
  if ((PMMIFG & SVMLIFG))
    while ((PMMIFG & SVMLVLRIFG) == 0);
  // Set SVS/SVM low side to new level
  SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
  // Lock PMM registers for write access
  PMMCTL0_H = 0x00;
}

Regards, Ryan

Hello Moshe,

I have seen such issue at some of the designs with MSP430F6736 due to RTCHOLD bit getting SET. When there is power loss, sometime MCU gets RESET first before getting power down and RTC may get stop due to RTCHOLD gets set at reset and code couldn't reach on the instruction where you are making it clear. However since you are using  MSP430F6736A, you can use RTCLOCK in your application. In your initialization code of RTC just set RTCLOCK bit in RTCCTL3.

For MSP430F6736 (without A), I would recommend below low level init function  for this issue:

For CCS compiler:

int _system_pre_init(void)

{

 //clear RTC

  RTCCTL0_H=RTCKEY_H; //unlock RTC_C Module

  RTCCTL13 &=~(RTCHOLD);

  RTCCTL0_H=0;

  return 1;

}

For IAR compiler:

int __low_level_init(void)

{

 //clear RTC

  RTCCTL0_H=RTCKEY_H; //unlock RTC_C Module

  RTCCTL13 &=~(RTCHOLD);

  RTCCTL0_H=0;

  return 1;

}

 Regards,

Vikas Chola

Hi Ryan

thanks for all your input Ryan.

Ideally i need to set RTCLOCK just before the POR is triggered...is there a mechanism in MCU (or userguide) to do that (i dont believe there is).

cheers

moshe