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MSP430F5418A: Watchdog timeout results reset with cause of SVSH POR

Sergey Markov
Intellectual 510 points
Part Number: MSP430F5418A

My configuration is:

PMMCTL0_H = PMMPW_H;
PMMRIE = SVSHPE;
SVSMHCTL = SVSHE;
SVSMLCTL = 0;

SVSH enabled, POR generation by SVSH enabled, all others SVS and SVM disabled.

My problem is: when WDT overflows, reset is generated, but SYSRSTIV register contains only one SVSH (0x0E) code instead of WDT time out (0x16) code. How to use watchdog timer together with SVSH in normal mode with POR generation by SVSH enabled? Why SVSH generates POR in result of WDT's PUC?

  • 0
    TI__Genius 15370 points

    Hi Sergey,

    The SYSRSTIV register has an output that is based on the priority of the interrupt event. Table 6-5 of MSP430F543xA, MSP430F541xA Mixed-Signal Microcontrollers shows that the SVSH interrupt vector has a higher priority than the WDT interrupt vector. You can read the SYSRSTIV multiple times to reveal all the different interrupt vector events that have occurred. For example, if a SVSH interrupt event and a WDT interrupt event both occur, the first time the SYSRSTIV is read will return 0x0E(SVSH). Then the second time it will return 0x16(WDT).

    So what's happening in your system is that you are getting a SVSH interrupt event AND a WDT event. I would double check that you are setting up the SVSH appropriately by referencing the example code as well as the Power Management Module and Supply Voltage Supervisor  section of MSP430x5xx and MPS430x5xx Family User's Guide.

    Best regards,

    Caleb Overbay

  • 0 in reply to Caleb Overbay
    Intellectual 510 points

    I know that SYSRSTIV can contain more than one value. More info: SYSRSTIV contains only ONE code, SVSH, when WDT generates reset from LPM3, but here is no any cause for real SVSH event. When WDT timeouts in active mode, all is OK, i see WDT TIMEOUT.

  • 0 in reply to Sergey Markov
    TI__Genius 15370 points
    Hi Sergey,

    Can you provide code that contains the minimum amount of operations to recreate the issue so I can test it out on my setup?

    Best regards,
    Caleb Overbay
  • 0 in reply to Caleb Overbay
    Intellectual 510 points
    No, i can't. This is not stable behavior over temperature and number of different chips. More info - with SVSMHCTL = SVSHE + SVSHMD; here isn't any problems. I think that this is related to PMM15 (or maybe also PMM11/12) errata. Because of this errata using SVSH in normal mode with SVSL/SVML disabled is impossible w/o SVSHMD bit is set, i think, that my question is closed.

    I guess, that after WDT PUC, SVSH initiates POR due to wakeup slower that 2us guard interval and SVSHPE bit set in PMMRIE, and clears WDT event from SYSRSTIV. If SVSH isn't shutdown while LPM3 sleeps, there is no problems.
  • 0 in reply to Sergey Markov
    TI__Genius 15370 points
    Hi Sergey,

    I think this could also be related to PMM9. Have you tried the workarounds specified for the errata mentioned? What were the results?

    Best regards,
    Caleb Overbay
  • 0 in reply to Caleb Overbay
    Intellectual 510 points

    Yes, PMM9 is more similar to this behavior than PMM15 and 11.

    After I added SVSHMD = 1 to SVSH configuration, after whole day of intensive testing on more than 10 devices no abnormal events was detected. SVSHMD=1 adds about 1.2 uA to device's power consumption, but this is not significant for me, since the total power consumption of the device is much larger.

  • 0 in reply to Sergey Markov
    TI__Genius 15370 points
    Hi Sergey,

    Glad to hear the PMM9 workaround has fixed the issue. I'll be closing this thread if you don't have any other questions or concerns.

    Best regards,
    Caleb Overbay

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