MSP430FR5994: I2C unable to receive from slave

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//******************************************************************************
//  MSP430FR231x Demo - eUSCI_B0 I2C Master TX bytes to Multiple Slaves
//
//  Description: This demo connects two MSP430's via the I2C bus.
//  The master transmits to 4 different I2C slave addresses 0x0A,0x0B,0x0C&0x0D.
//  Each slave address has a specific related data in the array TXData[].
//  At the end of four I2C transactions the slave address rolls over and begins
//  again at 0x0A.
//  ACLK = REFO = 32768Hz, MCLK = SMCLK = default DCO = ~1MHz
//  Use with msp430fr231x_uscib0_i2c_16.c
//
//                                /|\  /|\
//               MSP430FR2311      10k  10k     MSP430FR2311
//                   slave         |    |        master
//             -----------------   |    |   -----------------
//            |     P1.2/UCB0SDA|<-|----|->|P1.2/UCB0SDA     |
//            |                 |  |       |                 |
//            |                 |  |       |                 |
//            |     P1.3/UCB0SCL|<-|------>|P1.3/UCB0SCL     |
//            |                 |          |                 |
//
//   Darren Lu
//   Texas Instruments Inc.
//   Oct. 2015
//   Built with IAR Embedded Workbench v6.30 & Code Composer Studio v6.1
//******************************************************************************

#include <msp430.h>
#include <stdint.h>
#include <stdbool.h>

unsigned char TXData[]= {0x5B};//read register address
unsigned char RXSData[10];

unsigned char TXByteCtr;
unsigned short value,value1;
unsigned char *pRXData = 0x0;                       // Pointer to RX data

uint16_t u16TxCount = 0;
uint16_t u16RxCount =0;

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;                         // Stop watchdog timer

    // Configure Pins for I2C
    P1SEL0 |= BIT2 | BIT3;                            // I2C pins

    // Disable the GPIO power-on default high-impedance mode
    // to activate previously configured port settings
    PM5CTL0 &= ~LOCKLPM5;

    pRXData = (unsigned char *) RXSData;
    // Configure USCI_B0 for I2C mode
    UCB0CTLW0 |= UCSWRST;                             // put eUSCI_B in reset state
    UCB0CTLW0 |= UCMODE_3 | UCMST|UCSYNC;                    // I2C master mode, SMCLK
   UCB0CTLW1 |= UCCLTO_1;                  // time_out 28ms
    UCB0BRW = 0x28;                                    // baudrate = SMCLK / 8
  //  UCB0TBCNT = 0x0002;                     // number of bytes to be received
   // UCB0I2CSA =113;              // configure slave address
    UCB0I2CSA =88;              // configure slave address
    UCB0CTLW0 &=~ UCSWRST;                            // clear reset register
   // UCB0IE |= UCTXIE0 | UCNACKIE|UCRXIE;                     // transmit and NACK interrupt enable
   // UCB0IE |= UCTXIE0 | UCRXIE|UCBIT9IE;
    UCB0IE |= UCTXIE0 | UCRXIE;

    //__bis_SR_register( GIE);               // Enter LPM0 w/ interrupts

    TXByteCtr = 0X00;                                    // Load TX byte counter
    u16TxCount = 1;
    while (UCB0CTLW0 & UCTXSTP);                      // Ensure stop condition got sent
    UCB0CTLW0 |= UCTR | UCTXSTT;                      // I2C TX, start condition
    __bis_SR_register(GIE);         // Enter LPM0 w/ interrupts


    while(1)                                               // Remain in LPM0 until all data
    {
        __delay_cycles(10000);
        __delay_cycles(10000);  // Put a break point here

    }

}
  
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = USCI_B0_VECTOR
__interrupt void USCIB0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_B0_VECTOR))) USCIB0_ISR (void)
#else
#error Compiler not supported!
#endif
{
  switch(__even_in_range(UCB0IV,USCI_I2C_UCBIT9IFG))
  {
        case USCI_NONE: break;                        // Vector 0: No interrupts break;
        case USCI_I2C_UCALIFG: break;
        case USCI_I2C_UCNACKIFG:
            UCB0CTL1 |= UCTXSTT;                      //resend start if NACK
          break;                                      // Vector 4: NACKIFG break;
        case USCI_I2C_UCSTTIFG: break;                // Vector 6: STTIFG break;
        case USCI_I2C_UCSTPIFG: break;                // Vector 8: STPIFG break;
        case USCI_I2C_UCRXIFG3: break;                // Vector 10: RXIFG3 break;
        case USCI_I2C_UCTXIFG3: break;                // Vector 14: TXIFG3 break;
        case USCI_I2C_UCRXIFG2: break;                // Vector 16: RXIFG2 break;
        case USCI_I2C_UCTXIFG2: break;                // Vector 18: TXIFG2 break;
        case USCI_I2C_UCRXIFG1: break;                // Vector 20: RXIFG1 break;
        case USCI_I2C_UCTXIFG1: break;                // Vector 22: TXIFG1 break;
        case USCI_I2C_UCRXIFG0:

            u16RxCount++;                      // Decrement RX byte counter
            *pRXData++= UCB0RXBUF;              // Multiple bytes left to receive
            if(u16RxCount==1)
            {
               // *pRXData++= UCB0RXBUF;              // Multiple bytes left to receive
                UCB0CTLW0|=UCTXSTP;
            }
            else
            {
            //    *pRXData++= UCB0RXBUF;              // Multiple bytes left to receive
            }



            break;                // Vector 24: RXIFG0 break;
        case USCI_I2C_UCTXIFG0:

            if (TXByteCtr < u16TxCount)
            {
                UCB0TXBUF=TXData[0];
            }
            else
            {


            //    UCB0TXBUF=TXData[0];
              //  __delay_cycles(422);
                // UCB0CTLW0 |= UCSWRST;                             // put eUSCI_B in reset state
               //   UCB0CTLW1 |= UCASTP_2;                  // Automatic stop generate
                //  UCB0CTLW0 &=~ UCSWRST;                            // clear reset register

                //  UCB0TBCNT = 0x0003;                     // number of bytes to be received

                  UCB0CTLW0 &= ~UCTR;
                  UCB0CTLW0 |= UCTXSTT;                      // I2C TX, start condition

            }
            TXByteCtr++;
          break;                                      // Vector 26: TXIFG0 break;
        case USCI_I2C_UCBCNTIFG: break;               // Vector 28: BCNTIFG
        case USCI_I2C_UCCLTOIFG: break;               // Vector 30: clock low timeout
        case USCI_I2C_UCBIT9IFG: break;               // Vector 32: 9th bit

        default: break;
  }
}
/*
value=UCB0STATW;
 value1=value & UCBCNT0;
 while(value1==0)
 {
     value=UCB0STATW;
     value1=value & UCBCNT0;
 }*/

//unsigned char TXData[7]= {0Xb0,0x5b,0x30,0xf8 };the first data in the array is the command you
// want to sent
//RXByteCtr is to define how many of receive data


#include <msp430.h>
#include <stdint.h>

unsigned char RXSData[10];        //Receive data buffer
unsigned char TXData[7]= {0Xb0,0x5b,0x30,0xf8 };//{device address*2,register address,Low 8bit data, high 8bit data}

unsigned char *pRXData = 0x0;                       // Pointer to RX data
uint16_t u16TxCount = 0;
uint16_t u16RxCount =0;

unsigned char TXByteCtr,Readmode,RXByteCtr=1;

static unsigned short crc8MakeBitwise(unsigned char CRC, unsigned char Poly, unsigned char *Pmsg, unsigned int Msg_Size);
int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;                         // Stop watchdog timer

// Configure GPIO
P1OUT &= ~BIT0; // Clear P1.0 output latch
P1DIR |= BIT0; // For LED
P5SEL0 |= BIT0 | BIT1;
P5SEL1 &= ~(BIT0 | BIT1);

    // Disable the GPIO power-on default high-impedance mode
    // to activate previously configured port settings
    PM5CTL0 &= ~LOCKLPM5;

    // Configure USCI_B0 for I2C mode
    UCB0CTLW0 |= UCSWRST;                             // put eUSCI_B in reset state
    UCB0CTLW0 |= UCMODE_3 | UCMST|UCSYNC;                    // I2C master mode, SMCLK
   // UCB0CTLW1 |= UCCLTO_1;                  // time_out 28ms
   // UCB0CTLW1 |= UCASTP_2;                  // Automatic stop generated
    UCB0BRW = 0x12;                                    // baudrate = SMCLK / 8
   // UCB0TBCNT = 0x0004;                     // number of bytes to be received
    UCB0I2CSA =0x004c;              // configure slave address
    UCB0CTLW0 &=~ UCSWRST;                            // clear reset register
   // UCB0IE |= UCTXIE0 | UCNACKIE|UCRXIE;                     // transmit and NACK interrupt enable
    UCB0IE |= UCTXIE0 | UCRXIE;



    while (UCB0CTLW0 & UCTXSTP);                      // Ensure stop condition got sent
    pRXData = (unsigned char *) RXSData;
    UCB0CTLW0 |= UCSWRST;                             // put eUSCI_B in reset state

  
    TXByteCtr = 0X00;                                    // Load TX byte counter
    u16TxCount = 1;
    Readmode=1;
    while (UCB0CTLW0 & UCTXSTP);                      // Ensure stop condition got sent
    UCB0CTLW0 |= UCTR | UCTXSTT;                      // I2C TX, start condition
    while(1)                                               // Remain in LPM0 until all data
    {
        __delay_cycles(10000);
        __delay_cycles(10000);
    }
 //   }

}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = USCI_B0_VECTOR
__interrupt void USCIB0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_B0_VECTOR))) USCIB0_ISR (void)
#else
#error Compiler not supported!
#endif
{
  switch(__even_in_range(UCB0IV,USCI_I2C_UCBIT9IFG))
  {
        case USCI_NONE: break;                        // Vector 0: No interrupts break;
        case USCI_I2C_UCALIFG: break;
        case USCI_I2C_UCNACKIFG:
            UCB0CTL1 |= UCTXSTT;                      //resend start if NACK
          break;                                      // Vector 4: NACKIFG break;
        case USCI_I2C_UCSTTIFG: break;                // Vector 6: STTIFG break;
        case USCI_I2C_UCSTPIFG: break;                // Vector 8: STPIFG break;
        case USCI_I2C_UCRXIFG3: break;                // Vector 10: RXIFG3 break;
        case USCI_I2C_UCTXIFG3: break;                // Vector 14: TXIFG3 break;
        case USCI_I2C_UCRXIFG2: break;                // Vector 16: RXIFG2 break;
        case USCI_I2C_UCTXIFG2: break;                // Vector 18: TXIFG2 break;
        case USCI_I2C_UCRXIFG1: break;                // Vector 20: RXIFG1 break;
        case USCI_I2C_UCTXIFG1: break;                // Vector 22: TXIFG1 break;
        case USCI_I2C_UCRXIFG0:
            u16RxCount++;                      // Decrement RX byte counter
            *pRXData++= UCB0RXBUF;              // Multiple bytes left to receive
            if(u16RxCount==RXByteCtr)
            {
               // *pRXData++= UCB0RXBUF;              // Multiple bytes left to receive
                UCB0CTLW0|=UCTXSTP;
            }
            else
            {
            //    *pRXData++= UCB0RXBUF;              // Multiple bytes left to receive
            }

            __delay_cycles(2);
            break;                // Vector 24: RXIFG0 break;
        case USCI_I2C_UCTXIFG0:




            if (TXByteCtr < u16TxCount)
            {
                UCB0TXBUF=TXData[TXByteCtr+1];
            }
            else
            {


            //    UCB0TXBUF=TXData[0];
              //  __delay_cycles(422);
                // UCB0CTLW0 |= UCSWRST;                             // put eUSCI_B in reset state
               //   UCB0CTLW1 |= UCASTP_2;                  // Automatic stop generate
                //  UCB0CTLW0 &=~ UCSWRST;                            // clear reset register

                //  UCB0TBCNT = 0x0003;                     // number of bytes to be received
                 if(Readmode==1)
                 {
                  UCB0CTLW0 &= ~UCTR;
                  UCB0CTLW0 |= UCTXSTT;                      // I2C TX, start condition
                 }
            }
            TXByteCtr++;


          break;                                      // Vector 26: TXIFG0 break;
        case USCI_I2C_UCBCNTIFG: break;               // Vector 28: BCNTIFG
        case USCI_I2C_UCCLTOIFG: break;               // Vector 30: clock low timeout
        case USCI_I2C_UCBIT9IFG: break;               // Vector 32: 9th bit
        default: break;
  }
}