This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/MSP432P401R: msp432p401r (Black boards), CCS Version: 6.1.1.00022

Part Number: MSP432P401R

Tool/software: Code Composer Studio

I have a number of the older msp432p401r (Black boards)

currently using  CCS Version: 6.1.1.00022

MSP432 Device Support Files    6.1.0.6    com.ti.ccstudio.msp432.emu.win32.feature.group    Texas Instruments

the issue is I love writing code directly, the problem is the syntax in the examples use this format

EUSCI_B0->CTLW0 |= EUSCI_B_CTLW0_SWRST;           // Remain eUSCI_B in reset state

while I'm used to code in this format

UCB0CTLW0 |= UCSWRST;                                                      /* Software reset enable */

I also have a problem with interrupts

in  msp432_startup.ccs.c  line 103

"     defaultISR,                             /* EUSCIB0 ISR               */

I change this to

EUSCIB0_IRQHandler

but also msp432p401r.h has an interrupt vector   

EUSCIB0_IRQn                = 20,     /* 36 EUSCIB0 Interrupt */

Why are there 2 different IRQ handlers   msp432_startup.ccs.c  and msp432p401r.h

now on to  NVIC

the new method uses

   // Enable eUSCIB0 interrupt in NVIC module
    NVIC->ISER[0] = 1 << ((EUSCIB0_IRQn) & 31);

old preferred

NVIC_ISER0 |= INTISR20;   // eUSCI_B0

taken from  msp432p401r_classic.h

#define INTISR20                    0x00100000 // eUSCI_B0

the real problem is when I do run the code, it never gets to the interrupt routine my code is below

been working on a routine just to initialize the slave device, but no luck, I also have a logic analyzer, I can see the start bit along with the slave address, then the clock goes low and hangs with TXing any data as if the Interrupt is never executed and the TXBUFFER is never loaded, due to the Interrupt not being handled. 

in-addition Lastly I get a ton of these warnings

Description    Resource    Path    Location    Type
#2120-D static function "EUSCIB0_IRQHandler" treated as extern because it was referenced but not defined    msp432_startup_ccs.c    /blk_sensor_version2    line 45    C/C++ Problem
#48-D incompatible redefinition of macro "ADDMASK_M" (declared at line 3160 of "C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r_classic.h")    .ccsproject    /blk_sensor_version2    line 13192, external location: C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r.h    C/C++ Problem
#48-D incompatible redefinition of macro "ADDMASK_OFS" (declared at line 3159 of "C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r_classic.h")    .ccsproject    /blk_sensor_version2    line 13191, external location: C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r.h    C/C++ Problem
#48-D incompatible redefinition of macro "ADDRX_M" (declared at line 3157 of "C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r_classic.h")    .ccsproject    /blk_sensor_version2    line 13189, external location: C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r.h    C/C++ Problem
#48-D incompatible redefinition of macro "ADDRX_OFS" (declared at line 3156 of "C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r_classic.h")    .ccsproject    /blk_sensor_version2    line 13188, external location: C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r.h    C/C++ Problem
#48-D incompatible redefinition of macro "AESBLKCNT_M" (declared at line 1619 of "C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r_classic.h")    .ccsproject    /blk_sensor_version2    line 9229, external location: C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r.h    C/C++ Problem
#48-D incompatible redefinition of macro "AESBLKCNT_OFS" (declared at line 1618 of "C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r_classic.h")    .ccsproject    /blk_sensor_version2    line 9228, external location: C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r.h    C/C++ Problem
#48-D incompatible redefinition of macro "AESBLKCNT0" (declared at line 1620 of "C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r_classic.h")    .ccsproject    /blk_sensor_version2    line 9219, external location: C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r.h    C/C++ Problem
#48-D incompatible redefinition of macro "AESBLKCNT1" (declared at line 1621 of "C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r_classic.h")    .ccsproject    /blk_sensor_version2    line 9220, external location: C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r.h    C/C++ Problem
#48-D incompatible redefinition of macro "AESBLKCNT2" (declared at line 1622 of "C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r_classic.h")    .ccsproject    /blk_sensor_version2    line 9221, external location: C:\ti_blk_ccs6\ccsv6\ccs_base\arm\include\msp432p401r.h    C/C++ Problem

//*****************************************************************************
//
// A0 P5.5*
// A1 P5.4*
// A2 P5.3
// A3 P5.2*
// A4 P5.1*
// A5 P5.0*
// A6 P4.7*
// A7 P4.6*
// A8 P4.5*
// A9 P4.4*
// A10 P4.3*
// A11 P4.2*
// A12 P4.1*
// A13 P4.0*
// A14 P6.1*
// A15 P6.0*
// A16 P9.1#
// A17 P9.0#
// A18 P8.7#
// A19 P8.6#
// A20 P8.5#
// A21 P8.4#
// A22 P8.3#
// A23 P8.2#
//
//
// I2C P1.6*
// I2C P1.7*
//
//		I2C to LCD
//		P0   P1   P2   P3                  P4   P5   P6   P7
//		RS   R/W  E    X   D0  D1  D2  D3  D4   D5   D6   D7
//
//****************************************************************************
//****************************************************************************

#include "msp.h"

void LCD_init(void);


volatile uint32_t TXData_x = 0x00;
volatile uint32_t TXData_y = 0x00;

uint32_t TXData[64];//
uint32_t TXData_value;//

uint32_t i = 0x0000;;//

void main(void)
{
	
    WDTCTL = WDTPW | WDTHOLD;           // Stop watchdog timer
    P1SEL0 |= BIT6 | BIT7;                // I2C pins P1.6=SDA   P1.7=SCL

    NVIC_ICPR0 = 0xFFFFFFFF;  // clr INT
    NVIC_ICPR1 = 0xFFFFFFFF;  // clr INT
    NVIC_ISER0 |= INTISR20;  //    1 << ((EUSCIB0_IRQn) & 31);      // Enable eUSCIB0 interrupt in NVIC module

    // Configure USCI_B0 for I2C mode
    LCD_init();

    UCB0CTLW0 |= UCSWRST; 		// hold in RST
    UCB0CTLW0 = UCSWRST | UCTR |UCMODE_3  | UCMST | UCSYNC | UCSSEL__SMCLK; // I2C, TX, Mstr
    UCB0CTLW1 |= UCASTP_1;  // stop sent after byte ctr value
    UCB0BRW = 0x001E;   // baudrate = SMCLK /30

    UCB0CTLW0 &= ~UCSWRST;		// clr RST hold

    UCB0IE |= UCTXIE0 | UCNACKIE; //  Enable interrupt

	__enable_interrupt();
	UCB0CTLW0 |= UCTXSTP;  // tx a STOP and try to restart
	for (i = 300; i > 0; i--);  // kill some time


	UCB0I2CSA = 0x27;   // slave address
	UCB0CTLW0 |= UCTXSTT;  // send a start


	while(UCB0STATW & 0x0010)    // check if bus is busy
	{
		__no_operation();  // for debug
	}

}

void LCD_init(void)  // using a A2004 LCD along with PCF8574 I2C to 8bit out
{
	TXData[0x00] = 0x22; // set to 4 bit
	TXData[0x01] = 0x02; // drop "E" to accept data
// now 4 bit  High then Low
	TXData[0x02] = 0x22;
	TXData[0x03] = 0x02;
	TXData[0x04] = 0x20;
	TXData[0x05] = 0x00;

	TXData[0x06] = 0x20;  // reset display
	TXData[0x07] = 0x00;
	TXData[0x08] = 0x21;
	TXData[0x09] = 0x01;

	TXData[0x0A] = 0xA4;  // A
	TXData[0x0B] = 0x84;
	TXData[0x0C] = 0xA1;
	TXData[0x0D] = 0x81;

	TXData[0x0E] = 0xA4;  // B
	TXData[0x0F] = 0x84;
	TXData[0x10] = 0xA2;
	TXData[0x11] = 0x82;

	TXData[0x12] = 0xA4;  // C
	TXData[0x13] = 0x84;
	TXData[0x14] = 0xA3;
	TXData[0x15] = 0x83;

	TXData[0x16] = 0xA4;  // D
	TXData[0x17] = 0x84;
	TXData[0x18] = 0xA4;
	TXData[0x19] = 0x84;

	TXData[0x1A] = 0xFFFF;  //   EOF
	TXData[0x1B] = 0xFFFF;
	TXData[0x1C] = 0xFFFF;
	TXData[0x1D] = 0xFFFF;

}


void EUSCIB0_IRQHandler(void)  // never get executed
{
	if(UCB0IFG & UCTXIFG0)  // TX buffer is empty
	{
		if (TXData[TXData_x] == 0xFFFF)
		{
			UCB0CTLW0 |= UCTXSTP; // tx a stop condition
			__no_operation();
		}
		else
		{
		UCB0TXBUF = TXData[TXData_x];  // load TX buffer with new value
		TXData_x++;
		}
	}

	if(UCB0IFG & UCNACKIFG)  // received a NACK
	{
		UCB0CTLW0 |= UCTXSTP;  // tx a STOP and try to restart
		for (i = 300; i > 0; i--);  // kill some time
	}

}

any help is appreciated

Regards

Roman

msp432_startup.ccs.c

  • Hello Roman,

    Which version of the SimpleLink MSP432 SDK are you using? I cannot find the file "msp432_startup.ccs.c" in the latest version of the SDK.

    Based on the warnings it looks like two header files are being called "msp432p401r.h" and "msp432p401r_classic.h" that are creating conflicting defines. You should either use the header files from the SDK or from CCS.

    Thanks,
    Sai
  • Hello Sai

    thanks for the quick response

    msp.h  -->  msp432p401r.h  -->  msp432p401r_classic.h    they refer to the next  " .h " file

    the "msp.h" refers to    "msp432p401r.h"

    code from  msp.h

    //****************************************************************************

    // MSP432 devices

    //****************************************************************************

    #if defined (__MSP432P401R__)

    #include "msp432p401r.h"

    //****************************************************************************

    // Failed to match a default include file

    //****************************************************************************

    msp432p401r.h refers to msp432p401r_classic.h

    code from msp432p401r.h

    // Remap MSP430 intrinsics to ARM equivalents

    #include "msp_compatibility.h"

    #include "msp432p401r_classic.h"

    code from  msp432_startup_ccs.c
    
    //*****************************************************************************
    //
    // Copyright (C) 2012 - 2014 Texas Instruments Incorporated - http://www.ti.com/
    //
    // Redistribution and use in source and binary forms, with or without
    // modification, are permitted provided that the following conditions
    // are met:
    //
    //  Redistributions of source code must retain the above copyright
    //  notice, this list of conditions and the following disclaimer.
    //
    //  Redistributions in binary form must reproduce the above copyright
    //  notice, this list of conditions and the following disclaimer in the
    //  documentation and/or other materials provided with the
    //  distribution.
    //
    //  Neither the name of Texas Instruments Incorporated nor the names of
    //  its contributors may be used to endorse or promote products derived
    //  from this software without specific prior written permission.
    //
    // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
    // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
    // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
    // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    //
    // MSP432 Family Interrupt Vector Table for CGT
    //
    //****************************************************************************
    
    #include <stdint.h>
    
    /* Forward declaration of the default fault handlers. */
    static void resetISR(void);
    static void nmiISR(void);
    static void faultISR(void);
    static void defaultISR(void);
    
    static void EUSCIB0_IRQHandler(void);
    
    
    /* External declaration for the reset handler that is to be called when the */
    /* processor is started                                                     */
    extern void _c_int00(void);
    
    
    /* Linker variable that marks the top of the stack. */
    extern unsigned long __STACK_END;
    
    
    /* External declarations for the interrupt handlers used by the application. */
    
    /* To be added by user */
    
    
    /* Intrrupt vector table.  Note that the proper constructs must be placed on this to  */
    /* ensure that it ends up at physical address 0x0000.0000 or at the start of          */
    /* the program if located at a start address other than 0.                            */
    #pragma DATA_SECTION(interruptVectors, ".intvecs")
    void (* const interruptVectors[])(void) =
    {
        (void (*)(void))((uint32_t)&__STACK_END),
                                                /* The initial stack pointer */
        resetISR,                               /* The reset handler         */
        nmiISR,                                 /* The NMI handler           */
        faultISR,                               /* The hard fault handler    */
        defaultISR,                             /* The MPU fault handler     */
        defaultISR,                             /* The bus fault handler     */
        defaultISR,                             /* The usage fault handler   */
        0,                                      /* Reserved                  */
        0,                                      /* Reserved                  */
        0,                                      /* Reserved                  */
        0,                                      /* Reserved                  */
        defaultISR,                             /* SVCall handler            */
        defaultISR,                             /* Debug monitor handler     */
        0,                                      /* Reserved                  */
        defaultISR,                             /* The PendSV handler        */
        defaultISR,                             /* The SysTick handler       */
        defaultISR,                             /* PSS ISR                   */
        defaultISR,                             /* CS ISR                    */
        defaultISR,                             /* PCM ISR                   */
        defaultISR,                             /* WDT ISR                   */
        defaultISR,                             /* FPU ISR                   */
        defaultISR,                             /* FLCTL ISR                 */
        defaultISR,                             /* COMP0 ISR                 */
        defaultISR,                             /* COMP1 ISR                 */
        defaultISR,                             /* TA0_0 ISR                 */
        defaultISR,                             /* TA0_N ISR                 */
        defaultISR,                             /* TA1_0 ISR                 */
        defaultISR,                             /* TA1_N ISR                 */
        defaultISR,                             /* TA2_0 ISR                 */
        defaultISR,                             /* TA2_N ISR                 */
        defaultISR,                             /* TA3_0 ISR                 */
        defaultISR,                             /* TA3_N ISR                 */
        defaultISR,                             /* EUSCIA0 ISR               */
        defaultISR,                             /* EUSCIA1 ISR               */
        defaultISR,                             /* EUSCIA2 ISR               */
        defaultISR,                             /* EUSCIA3 ISR               */
    	EUSCIB0_IRQHandler,                             /* EUSCIB0 ISR               */
        defaultISR,                             /* EUSCIB1 ISR               */
        defaultISR,                             /* EUSCIB2 ISR               */
        defaultISR,                             /* EUSCIB3 ISR               */
        defaultISR,                             /* ADC14 ISR                 */
        defaultISR,                             /* T32_INT1 ISR              */
        defaultISR,                             /* T32_INT2 ISR              */
        defaultISR,                             /* T32_INTC ISR              */
        defaultISR,                             /* AES ISR                   */
        defaultISR,                             /* RTC ISR                   */
        defaultISR,                             /* DMA_ERR ISR               */
        defaultISR,                             /* DMA_INT3 ISR              */
        defaultISR,                             /* DMA_INT2 ISR              */
        defaultISR,                             /* DMA_INT1 ISR              */
        defaultISR,                             /* DMA_INT0 ISR              */
        defaultISR,                             /* PORT1 ISR                 */
        defaultISR,                             /* PORT2 ISR                 */
        defaultISR,                             /* PORT3 ISR                 */
        defaultISR,                             /* PORT4 ISR                 */
        defaultISR,                             /* PORT5 ISR                 */
        defaultISR,                             /* PORT6 ISR                 */
        defaultISR,                             /* Reserved 41               */
        defaultISR,                             /* Reserved 42               */
        defaultISR,                             /* Reserved 43               */
        defaultISR,                             /* Reserved 44               */
        defaultISR,                             /* Reserved 45               */
        defaultISR,                             /* Reserved 46               */
        defaultISR,                             /* Reserved 47               */
        defaultISR,                             /* Reserved 48               */
        defaultISR,                             /* Reserved 49               */
        defaultISR,                             /* Reserved 50               */
        defaultISR,                             /* Reserved 51               */
        defaultISR,                             /* Reserved 52               */
        defaultISR,                             /* Reserved 53               */
        defaultISR,                             /* Reserved 54               */
        defaultISR,                             /* Reserved 55               */
        defaultISR,                             /* Reserved 56               */
        defaultISR,                             /* Reserved 57               */
        defaultISR,                             /* Reserved 58               */
        defaultISR,                             /* Reserved 59               */
        defaultISR,                             /* Reserved 60               */
        defaultISR,                             /* Reserved 61               */
        defaultISR,                             /* Reserved 62               */
        defaultISR,                             /* Reserved 63               */
        defaultISR                              /* Reserved 64               */
    };
    
    
    /* This is the code that gets called when the processor first starts execution */
    /* following a reset event.  Only the absolutely necessary set is performed,   */
    /* after which the application supplied entry() routine is called.  Any fancy  */
    /* actions (such as making decisions based on the reset cause register, and    */
    /* resetting the bits in that register) are left solely in the hands of the    */
    /* application.                                                                */
    void resetISR(void)
    {
        /* Jump to the CCS C Initialization Routine. */
        __asm("    .global _c_int00\n"
              "    b.w     _c_int00");
    }
    
    
    /* This is the code that gets called when the processor receives a NMI.  This  */
    /* simply enters an infinite loop, preserving the system state for examination */
    /* by a debugger.                                                              */
    static void nmiISR(void)
    {
        /* Fault trap exempt from ULP advisor */
        #pragma diag_push
        #pragma CHECK_ULP("-2.1")
    
        /* Enter an infinite loop. */
        while(1)
        {
        }
    
        #pragma diag_pop
    }
    
    
    /* This is the code that gets called when the processor receives a fault        */
    /* interrupt.  This simply enters an infinite loop, preserving the system state */
    /* for examination by a debugger.                                               */
    static void faultISR(void)
    {
        /* Fault trap exempt from ULP advisor */
        #pragma diag_push
        #pragma CHECK_ULP("-2.1")
    
        /* Enter an infinite loop. */
        while(1)
        {
        }
    
        #pragma diag_pop
    }
    
    
    /* This is the code that gets called when the processor receives an unexpected  */
    /* interrupt.  This simply enters an infinite loop, preserving the system state */
    /* for examination by a debugger.                                               */
    static void defaultISR(void)
    {
        /* Fault trap exempt from ULP advisor */
        #pragma diag_push
        #pragma CHECK_ULP("-2.1")
    
        /* Enter an infinite loop. */
        while(1)
        {
        }
    
        #pragma diag_pop
    }
    

  • 1) the struct approach is easier and more portable. for example, you can simply define a macro for the peripheral, write your code to that macro and then change the macro to a different peripheral (of the same class) and your code will work for that peripheral. handy when you want to repurpose your code from one timer to another timer, or one spi to another spi.

    2) if you see defaultISR in the start-up file, you are using an older compiler -> when msp432 was introduced, TI didn't provide a start-up file with dedicated vectors. upgrade your compiler will do.

    3) on nvic: look for nvic_enableirq() and nvic_disableirq() in the cmsis files. use them instead.

  • Hi Danny and Sai
    thanks for your help.

    Found the problem to my issue.
    On line #75 of my code from above
    UCB0CTLW0 |= UCTXSTP; // tx a STOP and try to restart

    this get set even though I START has not been initiated.
    I ordered and received a 8 bit logic analyzer. When I looked at the data, a START is send then the ADDRESS, the slave send a ACK then a STOP is immediately sent a Stop before any data is sent.

    I commented out this line #75 of code before the initial START, this resolve the problem.
    Basically a STOP can be set before a START is initiated

    basically this is what was happening

    Set a STOP // used this to make sure the I2C bus has stopped --> realized it does not work this way
    Set the Slave ADDRESS
    Send a START
    Load TXBUFF
    // Master send a START then the ADDRESS wait for Slave ACK
    Slave send ACK
    Naster Sends a STOP
    Data is not sent due to immediate STOP

    As for the Code I have about 10 of the MSP432P401r (black boards, wish limit me to version CCS 6.1.1 ) as they are no longer supported in the higher versions.
    Plus I a bit old school, the manual / documentation refers to classical version of the codes.
    there is no version that describe the new method, only in the examples codes, at times can be a bit confusing.

    Thanks for all your help Danny and Sai
    you folks are fantastic with the quick response.

    Regards
    Roman

**Attention** This is a public forum