MSP430FR2311: Question about MSP430FR2311 security

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//******************************************************************************
//  MSP430FR413x Demo - Software Poll P1.3, Set P1.0 if P1.3 = 1
//
//  Description: Poll P1.3 in a loop. Set P1.0 if P1.3 = 1, or reset P1.0.
//               By default, FR413x select XT1 as FLL reference.
//               If XT1 is present, the XIN and XOUT pin needs to be configured.
//               If XT1 is absent, REFO is automatically switched for FLL
//               reference.
//               XT1 is considered to be absent.
//  ACLK = default REFO ~32768Hz, MCLK = SMCLK = default DCODIV ~1MHz.
//
//              MSP430FR4133
//            ---------------
//        /|\|               |
//         | |               |
//         --|RST            |
//     /|\   |               |
//      --o--|P1.3       P1.0|-->LED
//     \|/   |               |
//           |               |
//
//   Darren Lu
//   Texas Instruments Inc.
//   July 2015
//   Built with IAR Embedded Workbench v6.30 & Code Composer Studio v6.1 
//******************************************************************************

#include <msp430.h>
#include<stdint.h>

#pragma RETAIN(JTAG_signatures)
#pragma DATA_SECTION(JTAG_signatures, ".jtagsignature")
 uint16_t JTAG_signatures[] = {0xAAAA, 0x0002};

void main(void)
{
    WDTCTL = WDTPW | WDTHOLD;               // Stop watchdog timer

    P1OUT &= ~BIT0;                         // Clear P1.0 output latch for a defined power-on state
    P1DIR |= BIT0;                          // Set P1.0 to output direction
    P1OUT |= BIT1;
    P1DIR &= ~BIT1;                         // Set P1.3 as input
    P1REN|=BIT1;

    PM5CTL0 &= ~LOCKLPM5;                   // Disable the GPIO power-on default high-impedance mode
    SYSCFG0=FRWPPW|0x0000;                                  // to activate previously configured port settings
 //   SYSCFG0&=0xff00;
    JTAG_signatures[0]= 0xaaaa;
    JTAG_signatures[1]= 0xaaaa;

    SYSCFG0=FRWPPW|0x03;

    while (1)                               // Test P1.3
    {
        if (P1IN & BIT1)
            P1OUT |= BIT0;                  // if P1.3 set, set P1.0
        else
        {
            P1OUT &=~BIT0;                      // Toggle P1.0 using exclusive-OR
            SYSCFG0=FRWPPW|0x0000;                                  // to activate previously configured port settings

            JTAG_signatures[0]= 0xffff;
            JTAG_signatures[1]= 0xffff;
            SYSCFG0=FRWPPW|0x03;

        }

        __delay_cycles(100000);
    }
}