Other Parts Discussed in Thread: MSP430F5437
Hi,
a customer is using the
And specifically the erase and write functions similar to the functions in
C:\TI\MSP430ProgrammingWithJTAG-slau320ad\slau320w\Replicator430X\JTAGfunc430X.c
void WriteFLASH_430X(unsigned long StartAddr, unsigned long Length, word *DataArray)
void EraseFLASH_430X(word EraseMode, unsigned long EraseAddr)
The intent is to write a 32KB segment of Flash in one go with this function.
The question is whether the a timing in the datasheet is violated using this type of WRITE function.
The Table "Flash Memory" on page 56 of the datasheet specificies a tCPT Cumulative Write Timing:
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes.
If we take a look at the WRITE function with the IR and DR shifts, we are concerned that these writes are much slower than tCPT required by the datasheet.
void WriteFLASH_430X(unsigned long StartAddr, unsigned long Length, word *DataArray)
{
word i; // Loop counter
unsigned long addr = StartAddr; // Address counter
word FCTL3_val = SegmentInfoAKey; // Lock/Unlock SegA InfoMem Seg.A, def=locked
HaltCPU();
ClrTCLK();
IR_Shift(IR_CNTRL_SIG_16BIT);
DR_Shift16(0x2408); // Set RW to write
IR_Shift(IR_ADDR_16BIT);
DR_Shift20(0x0128); // FCTL1 register
IR_Shift(IR_DATA_TO_ADDR);
DR_Shift16(0xA540); // Enable FLASH write
SetTCLK();
ClrTCLK();
IR_Shift(IR_ADDR_16BIT);
DR_Shift20(0x012A); // FCTL2 register
IR_Shift(IR_DATA_TO_ADDR);
DR_Shift16(0xA540); // Select MCLK as source, DIV=1
SetTCLK();
ClrTCLK();
IR_Shift(IR_ADDR_16BIT);
DR_Shift20(0x012C); // FCTL3 register
IR_Shift(IR_DATA_TO_ADDR);
DR_Shift16(FCTL3_val); // Clear FCTL3; F2xxx: Unlock Info-Seg.
// A by toggling LOCKA-Bit if required,
SetTCLK();
ClrTCLK();
IR_Shift(IR_CNTRL_SIG_16BIT);
for (i = 0; i < Length; i++, addr += 2)
{
DR_Shift16(0x2408); // Set RW to write
IR_Shift(IR_ADDR_16BIT);
DR_Shift20(addr); // Set address
IR_Shift(IR_DATA_TO_ADDR);
DR_Shift16(DataArray[i]); // Set data
SetTCLK();
ClrTCLK();
IR_Shift(IR_CNTRL_SIG_16BIT);
DR_Shift16(0x2409); // Set RW to read
TCLKstrobes(35); // Provide TCLKs, min. 33 for F149 and F449
// F2xxx: 29 are ok
}
IR_Shift(IR_CNTRL_SIG_16BIT);
DR_Shift16(0x2408); // Set RW to write
IR_Shift(IR_ADDR_16BIT);
DR_Shift20(0x0128); // FCTL1 register
IR_Shift(IR_DATA_TO_ADDR);
DR_Shift16(0xA500); // Disable FLASH write
SetTCLK();
// set LOCK-Bits again
ClrTCLK();
IR_Shift(IR_ADDR_16BIT);
DR_Shift20(0x012C); // FCTL3 address
IR_Shift(IR_DATA_TO_ADDR);
DR_Shift16(FCTL3_val | 0x0010); // Lock Inf-Seg. A by toggling LOCKA and set LOCK again
SetTCLK();
ReleaseCPU();
}
Regards,
--Gunter
