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[FAQ] CCS/MSP430F6736: SD24B results

Part Number: MSP430F6736

Tool/software: Code Composer Studio

Hi team,

I am using the following example code for SD24 converters from the resource explorer:

#include <msp430.h>
#include <stdio.h>

/* Array to store SD24_B conversion results */
unsigned int results[3];

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;               // Stop WDT

    SD24BCTL0 |= SD24SSEL_1;      // Select internal REF
    SD24BCTL0 |= SD24REFS;                                        // Select SMCLK as SD24_B clock source

    SD24BCCTL0 = SD24SNGL | SD24SCS_5;      // Single conversion, group 1
    SD24BCCTL1 = SD24SNGL | SD24SCS_5;      // Single conversion, group 1
    SD24BCCTL2 = SD24SNGL | SD24SCS_5;      // Single conversion, group 1

    SD24BIE |= SD24IE2;                     // Enable channel 2 interrupt

    __delay_cycles(0x3600);                 // Delay for 1.5V REF startup

    while (1)
    {
        SD24BCTL1 |= SD24GRP1SC;            // Set bit to start conversion
        __bis_SR_register(LPM0_bits | GIE); // Enter LPM0 w/ interrupts
        SD24BCTL1 &= ~SD24GRP1SC;           // Clear bit for next conversion
        __no_operation();                   // SET BREAKPOINT HERE
        printf("Result1: %d \n",results[0]);
        printf("Result2: %d \n",results[1]);
        printf("Result3: %d \n",results[2]);
    }
}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=SD24B_VECTOR
__interrupt void SD24BISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(SD24B_VECTOR))) SD24BISR (void)
#else
#error Compiler not supported!
#endif
{
    switch (SD24BIV)
    {
        case SD24BIV_SD24OVIFG:             // SD24MEM Overflow
            break;
        case SD24BIV_SD24TRGIFG:            // SD24 Trigger IFG
            break;
        case SD24BIV_SD24IFG0:              // SD24MEM0 IFG
            break;
        case SD24BIV_SD24IFG1:              // SD24MEM1 IFG
            break;
        case SD24BIV_SD24IFG2:              // SD24MEM2 IFG
            results[0] = SD24BMEMH0;        // Save CH0 results (clears IFG)
            results[1] = SD24BMEMH1;        // Save CH1 results (clears IFG)
            results[2] = SD24BMEMH2;        // Save CH2 results (clears IFG)
            break;
    }

    __bic_SR_register_on_exit(LPM0_bits);   // Exit LPM0
}

I am getting output results for 8-bit resolution. 

I have a few questions:

1) How do I change my reference voltage to external reference(=3V) ? If I use an external reference, do I have to make any extra connections of capacitor to the MCU?

2) How do I change the resolution from 8-bit to 10-bit?

3) Is there a way to change the internal reference from 1.15V(from datasheet) to 3V?

4) I have single ended inputs coming to the positive inputs of the SD24 ports. So I am connecting the negative inputs of all the 3 inputs to ground. Will this work?

Thank you,

Keval

  • Hi Team,

    I wanted to add one more point to the above question.
    When I provide 0V as an input, I get 128 as the digital output on the screen.
    Am I using a correct code? Is there an issue with the code?


    Thank you,
    Keval
  • Hello Keval,

    Have you had a chance to read through the MSP430x5xx and MSP430x6xx Family User's Guide yet? It will help answer most if not all of your questions. I would highly recommend reading through the sections related to the Sigma Delta ADC as a start. There are sections about the REF module as well. To figure out which modules the MSP430F6736 features, you can find them in the functional block diagram in the datasheet.

    Keval Desai said:
    When I provide 0V as an input, I get 128 as the digital output on the screen.
    Am I using a correct code? Is there an issue with the code?

    Section 29.2.7.3 Digital Filter Output in the User's Guide talks about left- or right-alignment and various modes that affect the output format. Please spend some time getting familiar with Table 29-3. Data Format Example as well. Looking at your code from the code example, I see that the SD24 has the default offset binary mode (SD24DFx = 0) and right-aligned (SD24ALGN = 0) configuration. Now, looking at Table 29-3 below, you can see why you're (correctly) measuring 128 for a 0V input. However, 128 in decimal equals 0x80 in hexadecimal. This tells me without looking at the code above that you're just reading SD24BMEMHx and not both SD24BMEMHx and SD24BMEMLx. Thus, there isn't an issue with the code.

    For future reference, code is much more readable when posted to the forum using the Syntax Highlighter tool (looks like "</>") found under the "Insert Code, Attach Files and more..." link shown after you click the "Reply" button.

    Regards,

    James

    MSP Customer Applications

  • Hi James,

    I have gone through the user guide. I have solved the issue regarding the 0V=128 digital value by changing the SD24DFx bit and the reference voltage as well.

    But I am unable to get the 10-bit resolution for the outputs. How do I achieve that?

    Thank you,

    Keval

  • James Evans said:
    This tells me without looking at the code above that you're just reading SD24BMEMHx and not both SD24BMEMHx and SD24BMEMLx.

    Did you see this comment? Also, why are you referring to "10-bit" output? This is a 24-bit Sigma Delta ADC, not a 10-bit SAR ADC.

    Regards,

    James

    MSP Customer Applications

  • Hi James,

    Right now, I am only able to store the result in either, SD24MEMHx or SD24MEMLx, one at a time.
    And thus when I read from that particular SD24MEM register, I am getting an output equivalent to 8-bit resolution.
    How do I store the channel results into both the Hx and Lx registers together and read data from both of them?

    Thank you,
    Keval
  • Hello Keval,

    You'll want to store the results from (not in) SD24MEMHx, shift the result to the left by 16, and then concatenate this value with SD24MEMLx similar to what's done in the SD24BISR in the MSP430F673X_SD24B_06.c code example.

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     *******************************************************************************
     * 
     *                       MSP430 CODE EXAMPLE DISCLAIMER
     *
     * MSP430 code examples are self-contained low-level programs that typically
     * demonstrate a single peripheral function or device feature in a highly
     * concise manner. For this the code may rely on the device's power-on default
     * register values and settings such as the clock configuration and care must
     * be taken when combining code from several examples to avoid potential side
     * effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
     * for an API functional library-approach to peripheral configuration.
     *
     * --/COPYRIGHT--*/
    //*****************************************************************************
    //  MSP430F673x Demo - SD24_B, Single Conversion on a Single Channel Using ISR
    //                     with 24 bit Result
    //
    //  Description: This program uses the SD24_B module to perform a single
    //  conversion on a single channel. An SD24_B interrupt occurs when a
    //  conversion has completed. Test by applying a voltage to channel 2
    //  (SD2P0, SD2N0) and setting a breakpoint at the line indicated below.
    //  Run program until it reaches the breakpoint, then use the debugger's
    //  watch window to view the conversion result. Results (entire 24 bits)
    //  for channel 2 are stored in variable "results".
    //  ACLK = n/a, MCLK = SMCLK = DCO =  ~ 1.1MHz
    //  //* For minimum Vcc required for SD24_B module - see datasheet          *//
    //  //* 100nF cap between Vref and AVss is recommended when using 1.5V REF  *//
    //
    //  NOTE: Example intended to display method to retrieve the full 24 bit result
    //        value, not how to attain 24-bit accuracy from SD24_B module.
    //
    //                MSP430F673x
    //             -----------------
    //         /|\|              XIN|-
    //          | |                 |
    //          --|RST          XOUT|-
    //            |                 |
    //    Vin+ -->|SD2P0            |
    //    Vin- -->|SD2N0            |
    //            |                 |
    //            |            VREF |---+
    //            |                 |   |
    //            |                 |  -+- 100nF
    //            |                 |  -+-
    //            |                 |   |
    //            |            AVss |---+
    //            |                 |
    //
    //  M. Swanson
    //  Texas Instruments, Inc
    //  December 2011
    //  Built with CCS Version: 5.1.0 and IAR Embedded Workbench Version: 5.40.1
    //*****************************************************************************
    #include <msp430.h>
    
    /* Unsigned integer to store SD24_B conversion result */
    unsigned long results;
    
    int main(void)
    {
        WDTCTL = WDTPW | WDTHOLD;                       // Stop WDT
    
        SD24BCTL0 = SD24REFS | SD24SSEL_1;              // Select internal REF
                                                        // Select SMCLK as SD24_B clock source
    
        SD24BCCTL2 |= SD24SNGL;                         // Single conversion
    
        SD24BINCTL2 |= SD24INTDLY0;                     // Interrupt on 3rd sample
        SD24BIE |= SD24IE2;                             // Enable channel 2 interrupt
    
        __delay_cycles(0x3600);                         // Delay for 1.5V REF startup
    
        while (1)
        {
            SD24BCCTL2 |= SD24SC;                       // Set bit to start conversion
            __bis_SR_register(LPM0_bits | GIE);         // Enter LPM0 w/ interrupts
            __no_operation();
            __no_operation();                           // SET BREAKPOINT HERE
        }
    }
    
    #if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
    #pragma vector=SD24B_VECTOR
    __interrupt void SD24BISR(void)
    #elif defined(__GNUC__)
    void __attribute__ ((interrupt(SD24B_VECTOR))) SD24BISR (void)
    #else
    #error Compiler not supported!
    #endif
    {
        switch (SD24BIV)
        {
            case SD24BIV_SD24OVIFG:                     // SD24MEM Overflow
                break;
            case SD24BIV_SD24TRGIFG:                    // SD24 Trigger IFG
                break;
            case SD24BIV_SD24IFG0:                      // SD24MEM0 IFG
                break;
            case SD24BIV_SD24IFG1:                      // SD24MEM1 IFG
                break;
            case SD24BIV_SD24IFG2:                      // SD24MEM2 IFG
                results = SD24BMEMH2;                   // Save CH2 results (clears IFG)
                results = (results << 16) | SD24BMEML2; // Concatenate lower and upper words
                break;
        }
    
        __bic_SR_register_on_exit(LPM0_bits);           // Exit LPM0
    }
  • Thank you so much James.
    Appreciate it.

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