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MSP430F5438: External reset supervisor preventing communication over JTAG interface

Jack Goodyear
Prodigy 80 points
Part Number: MSP430F5438

I use an external reset supervisor to provide a more constrained reset voltage than that provided by the MSP's SVS.

The use of an external reset supervisor, push-pull output, 200ms reset timeout period is preventing communication over the JTAG interface for debugging the MSP430F5438A in Code Composer.

If I bypass the chip communication is successful.

Oscilloscope trace comparisons suggest the MSP430 expects the reset line to be pulled up quicker than the reset supervisor can achieve.

The supervisor has a manual reset input, meaning it can be put into reset by the MSP-FET430UIF debugging interface.

However, the RESET timeout of the supervisor chip is 200ms, and this appears to violate the JTAG protocol which briefly pulls the RST line to 0 (1ms or so).

1. Does the theory of the reset line being pulled low for too long sound plausible?

2. Is there a configuration setting in Code Composer Studio in which I can compensate for the additional delay in the reset signal?

3. Is this a common problem when using external reset supervisors, and is there a 'rule of thumb' or 'standard' solution?

I beliieve this can be solved in hardware, using a logical AND IC taking the MSP-430FETUIF RESET line and the external reset supervisor signal as inputs, but I'd rather avoid additional componentry.

Thanks in advance.

  • 0
    TI__Guru 56685 points
    Hello Jack,

    Let Me see if I can answer your questions here.

    1. I'm not sure by what you mean by this, but I think im confused on how exactly how you have your circuit. Are you trying to feed the Reset line output from the FET through the supervisor? If so, then this would definitely inhibit proper communication via JTAG. From a circuit perspective, there should not be anything between the FET and the MSP430 other than the recommended passive configuration.

    2. No there is not a setting within CCS for this. Most of the protocol is defined in HW within the JTAG module fo the chip itself. Its fairly tolerant but the delay you are imposing seem to be outside the limits.

    3. Typically, external chip supervisors are not used with this family of devices as the SVS covers most scenarios. Supervisor ICs are more common with our family of devices that do not have an SVS. in these cases, the programming of the device is either typically done by the CM using a socket before being placed on the board, the Supervisor IC is bypassed during programming somehow, or programming is done via the BSL interface (this still requires manipulation of RST line, but only to get into the BSL, or most parts have alternative ways of entering BSL as well that avoids the RST line).

    So to avoid additional components I would suggest either using the on board SVS, have the chips programmed before being reflowed onto the board, or use the BSL interface to program the chip.

    Can you elaborate more on why the SVS on the device does not fit your needs?

    Having your CM or distributor pre-program the parts before placing them on board is a popular solution.

    As for the BSL, this device can be placed into BSL mode from the typical TST + RST toggle entry sequence and via SW entry. Unfortunately, this particular family does not enter BSL automatically if it is a blank device. This family does however, allow you to customize the BSL including changing the entry sequence. So it is possible for you to change the entry sequence to check for a certain pin is high/low at startup or anything you want really. However, you would need to program the custom BSL into the chip at production, so it doesn't really solve your issue here, but could be a good path for in-system FW updates for you.
  • 0 in reply to Jace H
    Prodigy 80 points

    This confirms my suspicions.

    The issue I have is that the SVS range inbuilt into the MSP is to 2.50-2.9V so the MSP continues to enable chips at 2.5V which is a little low for a 3V3 supply. The next range up would potentially reset at levels too close to 3V3.

    An external reset supervisor constrains the reset level to 2.91V to 2.940V which provides more control. Hence I'd prefer to use an external supervisor.

    Your response has provided a lot of useful information and provides me with enough to go on at this stage. I will reconsider the design and use of the MSP SVS. Perhaps a fast enough switching logic AND gate will do the trick.


    Cheers,

    Jack

  • 0 in reply to Jack Goodyear
    TI__Guru 56685 points
    Jack,

    If I'm understanding you correctly, the MSP430 is enabling other chips in your system that are only tolerant to operate at 3.3V rail (with margin) before they are ready due to the MSP430 SVS?

    If so, you can setup the SVM to interrupt you when the power is raised to a sufficient level for your needs. at that point you could increase the speed of the MSP430 and/or enable the other chips in your system.

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