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MSP430F5437: difference between TA1 and TB0 when running in UP mode

Part Number: MSP430F5437
Other Parts Discussed in Thread: MSP430F5529, MSP430F5438A

Hello TI Forum,

I've noticed a difference between TA1 and TB0 when running in UP mode, and TOGGLE ouput pin mode.

Both timers use identical configurations (exactly as shown below), but the output pin frequencies I get from these two timers are not identical. 

 

TA1CCR0 = 9;

TA1CCTL1 = 0x0080;            //TA1.1 in compare mode and TOGGLE output pin mode

TA1CCR1 = 5;

TA1EX0 = 0x0000;                //TMRA1 input divider expansion set to 1

TA1CTL = 0x0114;               

 

TB0CCR0 = 9;

TB0CCTL5 = 0x0080;              //TB0.5 in compare mode and TOGGLE output pin mode

TB0CCR5 = 5;

TB0EX0 = 0x0000;                //TMRB0 input divider expansion set to divide by 1

TB0CTL = 0x0114;    

 

Both timers are clocked from ACLK, which is in my case 14.7456MHz.

 

TA1.1 output pin frequency (measured) is in line with the equation Fout = ACLK / ((TA1CCR0 + 1) * 2) = 737.28KHz

 

However, TB0.5 output pin frequency (measured) is higher and equals 819.2KHz, which is in line with Fout = ACLK / (TB0CCR0 * 2) = 819.2KHz

 

If I configure  TB0CCR0 = 10, then both timers generate identical frequencies (737.28KHz) on respective output pins.        

 

Can you please explain this behavior?

  • Hey Ed,

    I wasn't able to find any documentation of this kind of behavior.

    Are you using a TI EVM or is this a custom board?
    Are you trying to run the timers in perfect sync with each other of just measuring the period of the output signals?
    Can you share the full firmware Timer firmware with me?

    Thanks,
    JD
  • Hello JD, I am gathering the information and will respond when appropriate.
    Thank you for your help in this matter.
  • Hi JD,

    To address your questions:

    1. For this matter I consulted the “MSP430x5xx and MSP430x6xx Family User's Guide”, SLAU208Q.
    On page 465, paragraph 17.2.3.1 indicates that the period of Timer_A in UP mode equals TAxCCR0 + 1.
    On page 486, paragraph 18.2.3.1, the same kind of information is provided for Timer_B in UP mode.
    Same as for Timer_A the period of Timer_B in UP mode equals TBxCL0 + 1.

    2. I’m using a custom board with an MSP430F5437A on it.

    3. I just need to generate two clock signals on timer output pins and set required periods on
    respective output pi no sync between the timers is required.
    The problem is that for some reason the period I get from Timer_B is not in line with TBxCL0 + 1
    (see above, answer to question 1.), while the period of Timer_A is exactly in line with TAxCCR0 + 1.

    Namely, with the Timer_A and the Timer_B output pins configured in TOGGLE mode, the respective
    output pi frequencies should be:
    Timer_A: Fpin = Fclk / ((TAxCCR0 + 1) * 2) Timer_B: Fpin = Fclk / ((TBxCL0 + 1) * 2)

    However, the frequency I measure on the output pin of Timer_B is slightly higher than expected and
    is in line with equation Fpin = Fclk / (TBxCL0 * 2), which deviates from the specs provided in the
    datasheets.


    4. Below is the full firmware configuration related to Timer_A and Timer_B.
    Both timers are clocked from ACLK and run in UP mode, with TA1.1 and TB0.6 output pins configured
    in
    TOGGLE mode.

    On TA1.1 output pin I need a clock which equals ACLK / 20, so I load value 9 into the TA1CCR0,
    which in fac does result in the TA1.1 output pin clock frequency of ACLK / 20 (measured on the
    board).

    On the other hand, on TB0.6 output pin I need a clock which equals ACLK / 18, so initially I loaded
    value 8 int the TB0CL0 (called TB0CCR0 in IAR Embedded Workbench) but it resulted in the TB0.6
    output pin clock of ACLK / 16 (measured on the board).
    After I changed TB0CL0 value to 9, the clock frequency on the TB0.6 output pin was set to ACLK / 18.

    In other words, firmware configurations of both timers are now 100% identical, yet they generate
    different out pin periods.

    Why is this happening? What am I missing here?

    //ACLK = 14745600Hz
    //Config TA1.1
    TA1CCR0 = 9; //TMRA1 output pin frequency = ACLK / ((9 + 1) * 2) = 737.28KHz
    TA1CCTL1 = 0x0080; //TA1.1 in compare mode and TOGGLE output pin mode
    TA1CCR1 = 5;
    TA1EX0 = 0x0000; //TMRA1 input divider expansion set to divide by 1
    TA1CTL = 0x0114; //TMRA1 in UP mode, clock source ACLK ; input div 1 ; clear timer and divider
    //Config TB0.6
    //NOTE: register name TB0CCR0 is used in IAR EWB, and it corresponds to TB0CL0 used in TI’s SLAU208Q
    TB0CCR0 = 9; //TMRB0 output pin frequency = ACLK / (9 * 2) = 819.2KHz) ?????
    TB0CCTL6 = 0x0080; //TB0.6 in compare mode and TOGGLE output pin mode
    TB0CCR6 = 5;
    TB0EX0 = 0x0000; //TMRB0 input divider expansion set to divide by 1
    TB0CTL = 0x0114; //TMRB0 in UP mode, clock source ACLK ; input div 1 ; clear timer and divider
  • I wrapped this code and ran it on an MSP430F5529 Launchpad, and the two waves seem to match exactly. They're even in sync, which I attribute to coincidence.

    The Launchpad doesn't have a 14MHz crystal, only a 4MHz, so the resulting frequency was 200kHz.And of course an F5529 isn't an F5437.

    I'm not sure what you and I are doing differently.

    #include <msp430.h> 
    
    void
    clk_init(void)
    {
        P5SEL |= (BIT4|BIT5);                     // XT1 (32kHz on LP)
        P5SEL |= (BIT2|BIT3);                     // XT2 (4MHz on LP)
        UCSCTL6 &= ~XT2OFF;                       // Enable XT2
        UCSCTL3 |= SELREF_2;                      // FLLref = REFO
                                                  // Since LFXT1 is not used,
                                                  // sourcing FLL with LFXT1 can cause
                                                  // XT1OFFG flag to set
        UCSCTL4 |= SELA_2;                        // ACLK=REFO,SMCLK=DCO,MCLK=DCO
    
        // Loop until XT1,XT2 & DCO stabilizes - in this case loop until XT2 settles
        do
        {
            UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
            // Clear XT2,XT1,DCO fault flags
            SFRIFG1 &= ~OFIFG;                      // Clear fault flags
        } while (SFRIFG1 & OFIFG);                   // Test oscillator fault flag
        UCSCTL6 &= ~XT2DRIVE0;                    // Decrease XT2 Drive according to                                              // expected frequency
        UCSCTL4 |= SELS_5 + SELM_5;               // SMCLK=MCLK=XT2
        UCSCTL4 = (UCSCTL4 & ~SELA_7)|SELA_5;       // ACLK=XT2
    
        return;
    }
    int
    main(void)
    {
    	WDTCTL = WDTPW | WDTHOLD;	// stop watchdog timer
    	clk_init();
    	//ACLK = 4000000Hz from Launchpad XT2 (ACLK = 14745600Hz originally)
    	//Config TA1.1
    	TA1CCR0 = 9; //TMRA1 output pin frequency = ACLK / ((9 + 1) * 2) = 737.28KHz
    	TA1CCTL1 = 0x0080; //TA1.1 in compare mode and TOGGLE output pin mode
    	TA1CCR1 = 5;
    	TA1EX0 = 0x0000; //TMRA1 input divider expansion set to divide by 1
    	TA1CTL = 0x0114; //TMRA1 in UP mode, clock source ACLK ; input div 1 ; clear timer and divider
    	P2SEL |= BIT0;  // P2.0 as TA1.1 per SLAS590N Table 6-47
    	P2DIR |= BIT0;
    	//Config TB0.6
    	//NOTE: register name TB0CCR0 is used in IAR EWB, and it corresponds to TB0CL0 used in TI’s SLAU208Q
    	TB0CCR0 = 9; //TMRB0 output pin frequency = ACLK / (9 * 2) = 819.2KHz) ?????
    	TB0CCTL6 = 0x0080; //TB0.6 in compare mode and TOGGLE output pin mode
    	TB0CCR6 = 5;
    	TB0EX0 = 0x0000; //TMRB0 input divider expansion set to divide by 1
    	TB0CTL = 0x0114; //TMRB0 in UP mode, clock source ACLK ; input div 1 ; clear timer and divider
    	P3SEL |= BIT6;  // P3.6 as TB0.6 per SLAS590N Table 6-48
    	P3DIR |= BIT6;
    	while (1)
    	{
    	    LPM0;
    	}
    	/*NOTREACHED*/
    	return 0;
    }
    

  • Hey Ed,

    Thanks for the additional information.  Glad to see Bruce was able to test on MSP430F5529 and there were not any issues there.

    I don't have any MSP430F5437A's, but I run the same test as Bruce on a MSP430F5438A Experimenter's board tomorrow.  The MSP430F5438A are related devices are should share this same exact peripheral. 

    I'll share those results tomorrow afternoon.  

    Thanks,

    JD

         

  • Hey Ed,

    I also ran this test on an MSP430F5438A Device on a target board and see no difference between TimerA and TimerB output.  This board doesn't have any crystals, so I just ran off the default clocks.  I tested both Aclk and SMclk. 

       

    I had to change the pins and removed the clk_init from the code that Bruce provide.  Here is mine:

    /**
     * main.c
     */
    int main(void)
    {
    	
    	WDTCTL = WDTPW | WDTHOLD;   // stop watchdog timer
     //   clk_init();
    
    	//ACLK = 4000000Hz from Launchpad XT2 (ACLK = 14745600Hz originally)
        //Config TA1.1
        TA1CCR0 = 9; //TMRA1 output pin frequency = ACLK / ((9 + 1) * 2) = 737.28KHz
        TA1CCTL1 = 0x0080; //TA1.1 in compare mode and TOGGLE output pin mode
        TA1CCR1 = 5;
        TA1EX0 = 0x0000; //TMRA1 input divider expansion set to divide by 1
        TA1CTL = 0x0114; //TMRA1 in UP mode, clock source ACLK ; input div 1 ; clear timer and divider
        P8SEL |= BIT6;  // P2.0 as TA1.1 per SLAS590N Table 6-47
        P8DIR |= BIT6;
        //Config TB0.6
        //NOTE: register name TB0CCR0 is used in IAR EWB, and it corresponds to TB0CL0 used in TI’s SLAU208Q
        TB0CCR0 = 9; //TMRB0 output pin frequency = ACLK / (9 * 2) = 819.2KHz) ?????
        TB0CCTL6 = 0x0080; //TB0.6 in compare mode and TOGGLE output pin mode
        TB0CCR6 = 5;
        TB0EX0 = 0x0000; //TMRB0 input divider expansion set to divide by 1
        TB0CTL = 0x0114; //TMRB0 in UP mode, clock source ACLK ; input div 1 ; clear timer and divider
        P4SEL |= BIT6;  // P3.6 as TB0.6 per SLAS590N Table 6-48
        P4DIR |= BIT6;
        while (1)
        {
            LPM0;
        }
    
        /*NOTREACHED*/
        return 0;
    }

    Also tested at 12MHz SMclk:

      

    Thanks,

    JD

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