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MSP430FR2433: XT1 Clock Operation and requirement for XT1OFFG Crystal Fault Interrupt

Part Number: MSP430FR2433
Other Parts Discussed in Thread: MSP430G2553

As someone who has designed many boards using the MSP430Gxxx series the MSP430FR2433 has several unknowns. I now have a new design working, but there are mysteries surround the XT1 clock and interrupts that it can cause.

I did find that I had to use the "do...while" loop shown in the msp430fr243x_cs_04.c example.  Without this code the 32,768 crystal will not lock to the correct frequency - why this is needed I do not understand?

Also show in that example there is an interrupt trap for XT1OFFG crystal faults - it has the same "do...while" loop for the crystal to stabilize and a reset of the XT1OFFG interrupt.

For my current design I have not added this interrupt trap, and the design seems to work fine.

Please explain why the MSP430FR2433 has these differences to the MSP430Gxxx series and is the interrupt trap needed for a reliable design using the MSP430FR2433. In my design the low power modes I use always has the XT1 oscillator operating.

  • Hi Larry,

    This is about the oscillator-fault fail-safe feature and the function of XT1OFFG bit.

    Firstly, please read the section 3.2.13 Fail-Safe Operation of MSP430FR4xx and MSP430FR2xx Family User's Guide. Then let me walk you through the code below with detailed explanation. After that you should have no problems understanding this topic.

    #include <msp430.h>
    
    int main(void)
    {
        WDTCTL = WDTPW | WDTHOLD;               // Stop watchdog timer
    
        P2SEL0 |= BIT0 | BIT1;                  // set XT1 pin as second function
        do
        {
            CSCTL7 &= ~(XT1OFFG | DCOFFG);      // Clear XT1 and DCO fault flag
            SFRIFG1 &= ~OFIFG;
        }while (SFRIFG1 & OFIFG);               // Test oscillator fault flag
    
        while(1){
            LPM4;
        }
    }

    At start-up,

    • XT1CLK is selected as the FLL reference by default (CSCTL3 = SELREF__XT1CLK)
    • XT1 pins are in general-purpose I/O (GPIO) mode rather than the XT1 mode
    • XT1 is not operating, or in other words, XT1 is faulty
    • XT1OFFG is set, and the FLL reference source is automatically switched to REFO

    After the execution of line 7: P2SEL0 |= BIT0 | BIT1

    • XT1 pins are in XT1 mode
    • XT1 is operating, but the fault bits remain set until software resets them, even if the fault condition no longer exists
    • FLL reference source is still REFO

    After the execution of line 11: SFRIFG1 &= ~OFIFG

    • The fault bits are cleared
    • FLL reference source is now XT1

    In conclusion, when XT1 is to be used, it is required to write the below code (for MSP430FR2433) at initialization.

        P2SEL0 |= BIT0 | BIT1;                  // set XT1 pin as second function
        do
        {
            CSCTL7 &= ~(XT1OFFG | DCOFFG);      // Clear XT1 and DCO fault flag
            SFRIFG1 &= ~OFIFG;
        }while (SFRIFG1 & OFIFG);               // Test oscillator fault flag

    Otherwise, MSP430 could be working well but it is actually REFO rather than XT1 being used in your clock system.

    By the way, you can also refer to section 5.2.7 Basic Clock Module+ Fail-Safe Operation of  MSP430x2xx Family User's Guide, and you can find it pretty different from the oscillator-fault fail-safe feature discussed above. That's where difference lies between MSP430FR2433 and MSP430G2553.

    Nevertheless, the attached code at section 5.2.7.1 Sourcing MCLK from a Crystal of  MSP430x2xx Family User's Guide, even though written in assembly, is interestingly very similar to the do-while part of the code discussed above.

  • So the really big difference is that if the circuit inside the MSP430FR2433 ever detects an XT1 crystal fault (power, temperature, shock) then the fault flag is set and ACLK switches from the crystal to the internal REFO clock. I assume this is the reason for the interrupt trap, to reset the fault so the Crystal clock is reselected after any fault. On the MSP430G series the crystal was selected by a register selection.

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