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MSP430F5437A: Chip reliability due to design error - VCore connected to DVCC and AVCC

Part Number: MSP430F5437A
Other Parts Discussed in Thread: ADS7924

Greetings,

We recently discovered a design error on a product that was manufactured in fairly low quantity (500-700 units) spread over a period of 8 years. The symptoms of that design error did not present themselves until recently in the production run.  Our mistake was connecting together DVCC, AVCC, and VCore together at +1.8V.  The symptoms were unreliable startup/POR/BOR.

The datasheet is very clear about VCore and our mistake is obvious: "VCORE is for internal use only. No external current loading is possible. VCORE should be connected to only the recommended capacitor value, CVCORE."

The products we delivered with this design mistake went through production testing consisting of temperature cycling and repeated power cycling for each unit. They were operating correctly and reliably until our recent production batch, and some delivered units have had many thousands of hours of operation.

My question is, does TI believe there to be a risk of IC failure due to this design mistake?  Is there a reasonable risk that the silicon of the MSP430 could become damaged from shorting VCore to the DVCC/AVCC pins and allowing operation?

Thank you!

  • Is there a reasonable risk that the silicon of the MSP430 could become damaged from shorting VCore to the DVCC/AVCC pins and allowing operation?

    Yes

    You are exceeding the maximum specs.

    Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.


    Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

  • Thank you, Peter, for your input.  Here is my concern:

    The Absolute Maximum Ratings do not speak specifically to this issue, at least not in the typical measures for absolute max range limits. There is a footnote to the "Voltage applied to any pin (excluding Vcore): -0.3V to VCC+0.3V" line that states VCore should not be externally loaded or have voltage applied.  However, it does not state at which voltage or current loading permanent damage may actually occur to the device. It's just a footnote to the general pin under/over voltage limits.

    The simple and convenient answer is to infer that there may be permanent damage at any level of DC loading or external voltage to VCore.  However, when it comes to determining the management of fielded products (e.g. recalls), it helps to be pretty confident that there is an actual risk before deciding on the solution.  For example, if the most likely risk was the the occasional malfunction of the supervisor/BOR circuits, then that's a lot different situation than the risk of hard IC failures.

    I think the only way to really answer this specific question is with inside information on the device operation. As a first time poster on E2E, I'm not sure if this is the right venue to ask something like this.

  • Hi, Brent, 

    The formal answer to your question is that any unexpected behavior may occur if the specification is violated. But I can help to do the analysis from engineering view of point. 

    Between DVCC and Vcore is a regulator built-in the MCU. You can get the block diagram from the Figure 2-2 of the MSPF5437A user's guide. 

    If the Vcore is connected to DVCC directly, the regulator will be bypassed. Vcore specification is typical 1.4v to typical 1.9v from the datasheet section 5.22. If the DVCC is greater than 1.9v, the internal loading circuit in Vcore domain will be broken or life cycle shortened. It seems you are power supplying DVCC and Vcore with 1.8v. So the MCU can still work. But the PSRR will be no effect since the LDO is by passed. 

    I think the Vcore setting in your firmware should be PMMCOREV=0, and the frequency you are running the MCU should be less than 8MHz. Right? You can check your setting for the Vsvsh_it-. I think it should be 1.57v~1.78v. From datasheet, V(dvcc_bor_it-) should be ~1.45v. Because the LDO is bypassed, the PSRR is no effect so that the noise ripple on the DVCC will be go to the internal Vcore domain logic circuit. If the ripple voltage drops down to the 1.78v, SVS may occur. If the ripple voltage drops to 1.45v, BOR may occur. Since the DVCC is easy to be interfered by external noise (ESD, EFT, RF, etc) if the board power management circuit is not well designed, the ripple noise on DVCC will be the source to cause the unreliable reset symptom you have seen on the boards (reset source can be SVS/POR/BOR). 

    From the information in user's guide and datasheet, we can see the potential risk as I mentioned above. But there are also uncertain risks since there is no disclosure for the internal circuit design of the MSP430F5437A. Due to this, we cannot do the fully risk assessment if no detailed review for the internal circuit design. 

    I hope my answer can help you on your questions. 

    Thanks and Best regards, 

    Lixin 

  • Hi Brent

    On second thought, your "unreliable startup/POR/BOR" may be related to the 1.8V supply.  

    Try using 2.2V if possible

  • Brent, 

    If using 2.2V to power supply, it is better to disconnect the Vcore from DVCC because of the operating specification of the Vcore. 

    Thanks, 

    Lixin 

  • Thank you, Lixin, for the analysis!

    To resolve this design mistake, we are considering cutting the PCB trace that connects VCore to the 1.8V VCC. The end effect would be that the VCore pin was 'floating'. This would keep VCore from being driven by the 1.8V supply but it then leaves VCore without the recommended capacitance (470nF or 10:1 Vcc_cap/VCore_cap ratio).  I've tested 5 assemblies at room temperature with the VCore trace cut with no VCore external capacitance, and they boot 100%.  It appears far more reliable that way than with VCore shorted to Vcc but is still a significant risk for stable performance over temperature and other operating conditions.

    We are currently investigating ways to rework the assemblies to add the proper capacitance on VCore.  Of course, the specific solution to that is outside the scope of this forum.

    Peter - I think using 1.8V VCC should be fine in my design as long as VCore is connected properly.  Bumping to 2.2V Vcc would likely allow for higher clock rates but isn't viable given other design constraints on the existing assembly.  But thank you for providing some ideas to consider for a future respin of the design.

  • Hi, Brent, 

    I am glad to see the test result on the 5 reworked boards shows far more reliable performance. I think it is right direction to cut off the PCB trace that connects Vcore to 1.8V VCC and try to add proper capacitor on Vcore trace.

    if you think the issue is resolved, please press the resolved button to close this thread. If you have more questions, please let us know or you also can open a new thread in case you want to know something else. 

    Best regards, 

    Lixin 

  • Hi, Brent, 

    Take look at http://e2e.ti.com/support/microcontrollers/msp430/f/166/t/762258 

    The characterization test data that is represented in the datasheet was only performed at 2.2V and 3V. Characteristics when operating below 2.2V cannot be guaranteed. Please keep in mind that if you are operating at 1.8V, there is also zero margin as 1.8V is the absolute minimum

  • Thanks, Peter!  I did not appreciate the risk in using 1.8V in terms of peripheral operation.  I do use an I2C link from the MSP430 at 1.8V to talk to the TI ADS7924 which is characterized at 1.8V VCC.  It hasn't given me issues yet (that I've noticed).  There are certainly a lot of tradeoffs to consider when managing parts with different voltage ranges but I'll try to avoid 1.8V for the MSP430 on my next designs.  I appreciate you pointing me to this link.

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