MSP430I2041: How to get continuous conversion result sets without interrupts

Hello Nick,

The MSP430i2041 works well when sampling continuously. One of the advantages of this mode is that the decimation filter stays full whereas when triggering the SD ADC module via software, the decimation filter won't be full which impacts the accuracy. Since you only need three ADC channels, have you considered the MSP430AFE253? Its clocking structure for the SD ADC should allow you to configure a 5kHz sampling frequency that can run continuously. This would be easier to accomplish and perhaps even more accurate (higher OSR?) than using software triggering on MSP430i2041. By the way, is your 5kHz sampling frequency a hard requirement?

Regards,

James

>The MSP430i2041 works well when sampling continuously. One of the
>advantages of this mode is that the decimation filter stays full

A very good point, sir.

>Since you only need three ADC channels, have you considered the
>MSP430AFE253?

I looked at the 'AFE and it mostly just seems older, slower, and
more expensive. :-)

>Its clocking structure for the SD ADC should allow you to configure
>a 5kHz sampling frequency that can run continuously.

As I mentioned before, we WANT to return results at a frequency
that is different from the sample frequency (and not by an integer
amount) to try to tune out periodic noise. (I haven't actually tried
this before, so it could turn out to be a bust.) Neither of these
chips has near enough horsepower to be doing any significant arithmetic
on the samples 5000 times per second.

I should note that the A#1 reason for selecting the i20x0 chip is
the ability of its A/D converter to measure differential inputs that
can go below AVSS. I don't know of any other manufacturer whose A/Ds
can do that! We know from experience that having to bias the inputs
to obtain such true bipolar behavior is HIGHLY PROBLEMATIC (particularly
where circuit board ground planes are concerned).

>is your 5kHz sampling frequency a hard requirement?

Yeah, pretty much. We are replacing an existing device that returns
samples at approximately that rate.

James, I like your point about the decimation filter staying full,
and you have changed my mind. I now plan to spend a microsecond or
so 8000 times per second eating an interrupt where I will simply
grab and store the latest set of conversion results. Another
interrupt 5000 times per second will tell me to grab the results from
memory (with interrupts locked out) and report them via UART. The
A/D conversion interrupts will add a microsecond or so of jitter to
my sample report packet rate, but I can live with that.

Thank you very much for your ideas, James. I will close this thread
after waiting one more day to see if anyone else wants to weigh in.

-eNick

That statement about me closing this thread by now is no longer
operative. :-)
I have tried the interrupt method, and I am getting strange bahavior.
Specifically, I am running the A/D converter continuously, using OSR_32
and getting an A/D interrupt every 31.4 microseconds, and I expected
an interrupt every 128 uS. Can anyone explain why I am getting the
interrupts so often? My code is shown below:

//Initialize the A/D converter
SD24CTL = SD24REFS; //use Internal Voltage-Reference
SD24CCTL0 |= SD24GRP | SD24DF | SD24OSR_32; //Channel #0 is grouped with the next channel, and 2s-complement
SD24CCTL1 |= SD24GRP | SD24DF | SD24OSR_32; //Channel #1 is grouped with the next channel, and 2s-complement
SD24CCTL2 |= SD24DF | SD24OSR_32; //Channel #2 is the Master-Channel, and 2s-complement
SD24CCTL2 |= SD24IE; //interrupt-enable
SD24CCTL2 |= SD24SC; //start A/D conversions (will run continuously)

#pragma vector=SD24_VECTOR
__interrupt void SD24_ISR(void)
{
TMP_INDICATOR_PORT |= TMP_INDICATOR_BITP; //turn the Temporary Indicator signal ON

SACount16 = SD24MEM0; //fetch the 16-bit result from Channel #0
TVCount16 = SD24MEM1; //fetch the 16-bit result from Channel #1
BVCount16 = SD24MEM2; //fetch the 16-bit result from Channel #2

TMP_INDICATOR_PORT &= ~TMP_INDICATOR_BITP; //turn the Temporary Indicator signal OFF
}

Since I am having trouble with the interrupt solution, and therefore may
have to resort to my original plan, I would like to note that my original
question in this thread was never actually answered. Specifically, none
of the documentation states that an overflow condition with a group of
A/D channels is an *atomic* operation. CAN a 3-channel simultaneous
overflow be INTERRUPTED by software trying to read three SD24MEMx registers?
I need three SIMULTANEOUS conversion results, even if they happen to be
stale. Note that locking out interrupts while the software tries to fetch
three SD24MEMx results would not help, becauce the overflow operation is
performed by the A/D HARDWARE. I need to know if the hardware overflow
operation on a group of channels is atomic or not. I'm hoping that TI
will GUARANTEE that the overflow is atomic. :-)

-eNick

The OSR field is a divisor, so OSR=32 means a period of (32/1024000)=31.25 usec. With OSR=128 it's (128/1024000)=125 usec, which sounds more or less like what you're looking for.

I've never seen a guarantee that all the MEM registers in a group are updated simultaneously. It's presumably "pretty close" but for all I know there's a serialization in the Verilog somewhere that throws it off by a microsecond or so. I do believe the IFGs, though.

If the plan is to always pick up the samples (that wasn't true in your original plan) you could use the OVIFG as an indicator -- read them all (per SD24IFG), then see if any of the OVIFGs is set. If so, you lost the race. (This would mean you're extremely late in the ADC cycle, and could be coded as "highly unlikely".)

[Edit: Fixed typo]

Very interesting. I have a similar case in which I need to digitize a 5 KHz signal (exactly) also on the three channels synchronously, with MSP430i2040. Mi concern is with what is described in Fig 13-5 of SLAU335 (page 330): Digital Filter Step Response and Conversion Points Digital Filter Output:: "For step changes at the input after start of conversion, a settling time must be allowed before a valid conversion result is available  ...  An asynchronous step requires four conversions before valid data is available"

I understand from this text and the figure that each conversion will have a memory of the previous 2 or 3 conversion. which may be negligible for slow varying signals but at 5 kHz may compress and/or distort the readings bigly.

Is there something I do not understand here? I also went through search of SAR parts but found out (the ones I looked at at least) that they use a multiplexer and single ADC - not good.

Or: is there a way to compensate, knowing the signal is a 5 kHz sine and some odd harmonics?

Using SD24INTDLY seems useless since the signal keeps moving...

Mac