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MSP430FR2433: Minimum SMCLK Frequency Required for 400KHz I2C Operation..

Part Number: MSP430FR2433

Hi Team '430,

The max SMCLK frequency for the FR2433 I2C peripheral is spec'd at 16MHz.  My customer wants to know the minimum SMCLK frequency required to run the FR2433 I2C peripheral at the max rate of 400KHz..

Reference: http://www.ti.com/lit/ds/symlink/msp430fr2433.pdf

Thanks, Merril

  • Thanks for your post.

    We will look into this and get back to you.

    Thanks,

    Yiding

  • Hello Mr. Newman,

    According to the user's guide section 24.3.7, the max bit rate for the I2C clock is BRCLK source / 4, which for this customer is  SMCLK / 4. 

    This means SMCLK could be as slow as 1.6MHz. to generate a 400Khz bit rate clock

    Assuming DCO = MCLK = 8Mhz, there is no divisor (DIVS) to scale the SMCLK down to 1.6Mhz.

    The closest DIVS = 4 would create a 2MHz SMCLK which could then be divided down by the UCBxBRW baud rate divisor = 5 to generate the 400Khz.

    If the customer is willing to run DCO = MCLK at a different frequency than 8Mhz, then there is probably several different combinations frequencies and divisors that could produce an SMCLK less than the 2Mhz.

  • Thank you Mr. Lehman.. As always I really appreciate your support!

    -Merril

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