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MSP430 UCS

Ben Walpole
Intellectual 790 points
Other Parts Discussed in Thread: MSP430F5419, MSP430F5438A

Hi,

I'm currently working with an MSP430F5419, I'm trying to get a handle on the UCS and in particular tuning the frequency of the DCO while using the FLL to stabilize it. Are there any aplication notes and/or examples with regard to this?

  • 0
    Guru 227245 points

    Programming the UCS is really straight.
    Anyway, there is a sourcecode library that contains HAL functions for setting the UCS. You can check the code for what it does.

    It is, however, really not difficult to figure it out yourself. The FLL does most of the job automatically. All you have to do is to select a proper RSEL fo rthe rough frequency range, program the reference frequency and the scaling factor and then wait until the FLL has pushed the DCO to the desired frequency.

     

  • 0 in reply to Jens-Michael Gross
    Intellectual 790 points

    Jens-Michael Gross said:

    Programming the UCS is really straight.
    Anyway, there is a sourcecode library that contains HAL functions for setting the UCS. You can check the code for what it does.

    It is, however, really not difficult to figure it out yourself. The FLL does most of the job automatically. All you have to do is to select a proper RSEL fo rthe rough frequency range, program the reference frequency and the scaling factor and then wait until the FLL has pushed the DCO to the desired frequency.

     

    Well anything is straight forward once you know how, all I was looking for was a bit of guidance.

     

     

  • 0 in reply to Ben Walpole
    Guru 227245 points

    Ben Walpole said:
    Well anything is straight forward once you know how

    That's only too true :)

    Ben Walpole said:
    all I was looking for was a bit of guidance

    The users guide explains almost everything. Yet I must admit that it is sometimes too detailed where you don't want it and not detailed enough where you'd like to have more info.

    Anyway, there is no general 'how to do it', as usage and programming of the UCS depends on what you want to achieve. This can go from 'ignore it and be happy with the defaults' up to complex background tasks for temperature-stabilizing a high-precision clock signal.

    You original question was how to tune the DCO frequency and stabilize it by the FLL. Maybe my answer was too short, but I think it was exhaustive. I can try onece more with more detail:

    • pick a destination frequency (e.g. 10MHz)
    • pick an RSEL setting that covers this frequency (the datasheet offers the information that RSEL_4 and RSEL_5 will  under worst cases cover 10MHz with a DCO setting > DCO_0 and < DCO_31 - pick one of them. Both can give differently good results, but which one is not predictable. DOCREL_3 or _6 may work too btu that' snot guaranteed for all devices)
    • Write this value to UCSCTL1
    • pick a reference clock source for the FLL. Easiest choice is REFO, the default it XT1CLK, which sould require a running watch crystal on XT1 - bu tif ther ei snone, the default selection will fallback to REFO. This setting is done in UCSCTL3
    • calculate the factor between the destination and the reference frequency (10MHz/32768Hz = 305)  and write it into the proper FLLN and FLLD bits in UCSCTL2 (in this case, clear the FLLD bits and just use 305 for FLLN)
    • now you'll have to wait until the FLL has adjusted the DCO to the destination frequency.This will take at most 32 ms (32 possible DCO setting and 32 modulations, one adjustment every REFO tick = 1024/32768 s). There's no way to know when the final values is reached, except for wating th emaximum time or checkign whther the DCO/MOD bits in UCSCTL0 still change
    • You can speed up this process by preloading the DCO registers with a value that appears a good guess, so the FLL does not take so long to do the adjustments, but this is optional.

    That's all. After at most 32ms, DCO, MCLK  and SMCLK are running on 10MHz. (the default for them is DCOCLKDIV, which is the current DCOCLK divided by the FLLD value, which is 0 in this case)
    ACLK is per default set to LFXT1, and falls back to REFO if there is no running crystal.

     

  • 0 in reply to Jens-Michael Gross
    Intellectual 790 points

    Thanks that exactly what I wanted, you've explained it in much clearer terms than it does in the user guide.

  • 0 in reply to Ben Walpole
    Guru 227245 points

    Ben Walpole said:
    Thanks that exactly what I wanted

    Fine. You're welcome.

    Ben Walpole said:
    you've explained it in much clearer terms than it does in the user guide.

    That's mostly because thsi explanation was for one specific usage/setup of the UCS module, while the users guide has to address everything, and for any device of the family (each with its own datasheet and specs), so it has to be more generic. This makes startup more difficult but greatly simplifies porting the code from one family member to another or even across families.

    It's however not as complicated as it might look at first. The only thing is that one cannot skip chapters in teh guide because they seem to be of no interest for the current task. That turns out as a big mistake otoo often, as all parts work together this or that way and wihtout understanding at elast the basics of one module, you cannot fully understand the other. Especially clock system and timers or timers and ADC or CPU core description and interrupt management for most other modules, etc.

  • 0 in reply to Jens-Michael Gross
    Prodigy 50 points

    I have an msp430f5438a and I like your article.  Using the defaults my clock is 1048576 Hz and I had the UART running at 9600 really good using your table 32.5 and a timer A1 toggling the output at a tad over 1kHz great stuff.  I have moved the clock up to 8388608 Hz with difficulty.  The default FLLN divide is 32 and FLLN default is 31=1Fh.  To get the higher clock FLLN divide should be 256 and FLLN should be set to FFh, this gave a toggle output at a tad over 4kHz,  setting FLLN = 1FFh should have given a 16k Hz output but is was still 4kHz.  I eventually set FLLD =0h the default is 1.  Now it all works great with the baud rate of 115200 again from table 35.2.  Are you sure that there are ten bits in FLLN as only seven of em seem to have any effect?  Great chip Ian.

  • 0 in reply to Ian Chapman
    Guru 227245 points

    Besides setting the FLL factor, you also have to pick the right frequency range for the DCO. If the selected (with UCSRSELx) frequency range only goes up to e.g. 6MHz and you tell the FLL to drive the DCO to 8MHz, the FLL will push it to the upper limit, but no more. The FLL can’t change the RSEL bits.
    This is partly intentional, so in case of a reference problem (e.g. during low-power modes), the FLL can’t push the DCO to unwanted heights, causing a crash.
    Note that different MSPs have different resulting DCO frequency ranges for the same RSEL settings. Your target frequency should be above the maximum frequency of the RSEL range for DCOX=0 and below the minimum for DCOx=31. See the tables in the datasheet.

    Also, yes, FLLD is 1 by default, running the DCO on twice the target frequency and dividing the DCOCLKDIV output by 2 (which is the default source for MCLK and SMCLK). This reduces the short-term clock jitter introduced by the modulation.

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