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MSP432P401R: Master mode SPI CLK duty cycle is not 50%

Raz Dan
Prodigy 50 points

Part Number: MSP432P401R

Hi,

Our MSP432P401R Rev D is connected to an SD card using an SPI interface. Our configuration values are shown below:

const eUSCI_SPI_MasterConfig spi_config = {
EUSCI_B_SPI_CLOCKSOURCE_SMCLK, // SMCLK Clock Source
48000000, //SMCLK is 48MHZ
16000000,
EUSCI_B_SPI_MSB_FIRST, // MSB First
EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT, // Phase
EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW, // Low polarity
EUSCI_B_SPI_3PIN // 3Wire SPI Mode
};

When I look at the CLK signal that is output from the MSP then it has the correct frequency (16MHz) but the duty cycle is not 50%.  The duty cycle is only 32% (20ns High, 42.5ns Low).  It seems that as a result of the incorrect duty cycle we are getting data corruption during reads from and writes to the SD card.  I've seen the same SPI CLK duty cycle issue reported multiple times in this support forum but I could not find one final solution to this problem.  Some responses from the TI support team (to the other postings in the forum) indicate that 24MHz is the maximum allowed value for the SMCLK but other responses from TI support indicate that it is OK to use 48MHz.  If it is impossible to get a 16MHz clock with the correct 50% duty cycle then can you please provide the correct values for the SMCLK and SPI CLK that will provide the maximum safe SPI CLK frequency.

Thanks,

Raz

  • 0
    Guru 88490 points

    I don't see a statement about SCK duty cycle as it pertains to BRCLK. There's a hint in the I2C section [Ref TRM (SLAU356I) Sec 26.3.6]

    I'm not too surprised though, since the eUSCI can't really work with a fractional system clock cycle. I expect if you use SCK=12MHz (BRW=4) you'll get a 50% duty by effectively extending the short part of the cycle you see now.

  • 0
    TI__Expert 7365 points

    Hi Raz,

    The duty cycle that you are seeing at 16 MHz is because of the divide ratio of 3. To get close to 50% duty cycle, I think you will need a divide ratio that is 1 or an even number.

    Raz Dan said:
    24MHz is the maximum allowed value for the SMCLK

    I think the responses from TI support is based on the note in the introduction to the clock system in section 6.1 of the TRM (https://www.ti.com/lit/pdf/slau356) - "SMCLK is limited in frequency to half of the rated maximum frequency of HSMCLK." While the maximum rated clock for these devices from the datasheet is around 48 MHz for DCO. You can see this in Table 5-12 of the Datasheet (https://www.ti.com/lit/gpn/msp432p401r).

    You can try SMCLK of 24 MHz and divide ratio of 1 or 2 to get the 50% duty cycle on the SPI clock.

    Srinivas

  • 0
    TI__Expert 7365 points

    Raz,

    Additionally, you can see section 4.2 "Calculating the Maximum SPI Communication Speed" of the app note "Solutions to Common eUSCI and USCI Serial Communication Issues on MSP430™ MCUs" at http://www.ti.com/lit/slaa734. It gives you the methodology of computing the maximum feasible clock rate based on the setup and hold time requirements of the device. The relevant timing characteristics for MSP432P401R can be found in Table 5-39 "eUSCI Switching Characteristics (SPI Master Mode)" of DS (https://www.ti.com/lit/gpn/msp432p401r). 

    Srinivas

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