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Migration expectations to TM4C part from LM3S part

During product development, we have identified a number of hardware related issues in the use of a Stellaris LM3S1811 MCP including the I2C bus hanging, flash only allowing 100 erase/write cycles, SPI can't be configured to the SPI mode needed by a 25C64 style SPI EEPROM, and a number of other issues that are specified in the datasheet that are noted in the errata (i.e. can't use the internal LDO for the core supply).  Do the Tiva TM4C123xxx series MCPs have these issues fixed?

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  • Guru 47900 points

    Applaud both your astuteness & bravery in so posting.  And - believe many here share (or should share) your interest.

    To encourage best/brightest/fastest factory response - suggest slight tweak to your post - as follows:

    a) I2C bus hanging - under what conditions, number of slaves, interconnect length, presence/activity of noise sources, I2C interrupts in use (yes/no), and usual time and/or frequency of such hang occurrences.  How have you established that any/all slaves have not, "co-conspirator" status?  And - have you noted this hang across multiple boards - multiple MCU revisions?  (belief is that this greater detail will encourage faster & more detailed vendor response)

    b) Flash issue likely confined to single "class" of past Stellaris M3.  (Tempest - iirc)  May they rest in NRND peace...

    c) SPI mode incompatible w/"multiple" 25Cxx style EEProms.  (you surely know that Stellaris specific mode - identification/presentation here saves time, wear/tear upon responders - accelerates response)

    d) Cross Reference charts now exist which guide you from past LX4F to rebrand device.  By survey - you may be able to "tighten" your request to specific, rebrand parts.

    e) Errata exists for several (most?) rebrand devices - your review of that & earlier LX4F errata seems worthwhile.  Careful comparison of errata between earlier LX4F and rebrand equivalent - may speak volumes to any/all tech activity/achievement - beyond rebrand exercise...

    Believe more specific questions may preclude vendor's famed response, "rebrand - production is ramping!"  Indeed - 1st silicon off the wafer meets that definition - yet long, long absence of vendor's devices from disty shelves requires tad more vendor care - and specificity - to effectively reply & comfort NRND masses...

  • Oliver,

    Per this post, it looks like you are currently working with a Stellaris LM3S1811-IQC50-C5 and are looking at the TM4C1231E6PZ as the TI recommended alternative.  I'll answer your questions here:

    1) I2C bus hardware lockup issues (not in errata for LM2S1811, but noted in forums)

    cb1 brings up some good points in his post above.  What conditions do you see the I2C bus hang?  Have you seen this personally or do you have a forum post that you can link to that describes the issue?

    2) erase/write cycles limited from 15,000 to 100 in errata, 

    The TM4C123 devices have a minimum specification of 100,000 program/erase cycles before failure (PECYC).  The TM4C1231E6PZ has a different Flash and, as cb_1 pointed out, this Flash does not have the same issue as the Flash on the LM3S1811.

    3) SPI limitation of hardware and drivers not supporting an Atmel AT25640B-MAHL-T SPI EEPROM frame polarity and timing.

    I am not sure what SPI mode you are referring to.  The TM4C1231E6PZ  data sheet can be found here.  You can look through the SSI section of this to figure out if these device has the correct modes you need.

    4) Vddc limitation of using internal LDO to required external LDO in rev C3 errata.

    The erratum “Flash corruption or device failure may occur at power on” was fixed in rev C5 of the LM3S1811 and is not present on the TM4C devices.

    I would recommend taking a look at the errata for the TM4C1231E6PZ which can be found here as well as the data sheet to see if this device meets your system's requirements.



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