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RTOS/TM4C1294NCPDT: TI-RTOS thread safe driver support

Harshel
Intellectual 955 points
Part Number: TM4C1294NCPDT

Tool/software: TI-RTOS

Hi,

I am developing an embedded application using TM4C1294NCPDT and TI-RTOS v2.16.

I need thread safe drivers for ADC, EEPROM, Flash, etc. peripherals for which TI-RTOS does not provide thread safe drivers as mentioned in TI-RTOS user guide.

I need support/guidance to developing thread safe drivers.

How can I start development of thread safe drivers for such peripherals ?

  • 0
    TI__Guru* 96960 points
    Hi Harshal,

    You have a couple options.
    1. Take a look at the I2C module and model the usage of Hwi_create and Semaphores to make the drivers thread-safe.
    2. Take a look at the SimpleLink MSP432E4 SDK (www.ti.com/.../SIMPLELINK-MSP432E4-SDK). This is a CortexM4F device also and the peripherals are the same. So look at the source\ti\drivers\adc (or adcbuf) high-level and low level drivers. For flash, there is NVS (Non Volatile Storage). There is not one for EEPROM.

    Todd
  • 0 in reply to ToddMullanix
    Intellectual 955 points
    Hello Todd,
    thanks for immediate reply.
    Can I use state machine implementation for I2C with few modifications ? (due to copyright act)

    Also EEPROM and Flash shares same interrupt, so what is best solution to manage such scenario.
  • 0 in reply to Harshel
    TI__Guru* 96960 points

    The BSD license allows you modifying the code. You just need to keep the banner in the file.

    harshal patil said:
    Also EEPROM and Flash shares same interrupt, so what is best solution to manage such scenario.

    That's a little too broad of a question. I'm not sure what you goal is. 

  • 0 in reply to ToddMullanix
    Intellectual 955 points
    In TM4C1294NCPDT, EEPROM and flash share same interrupt number. If I have to develop drivers for EEPROM and Flash interrupt configuration for hwi is same and interrupt handler will also be same. So for such implementation, what should be best possible way of implementation ?
  • 0 in reply to Harshel
    TI__Guru* 96960 points
    I'd have the one ISR manage both functionalities. You need to figure out how it knows what to do. For example, don't let EEPROM and Flash actions happen at the same time, so the ISR knows what to do.

    Todd