Hi,
I have just started attempting to implement EPI SRAM on our LM3S9B96 modules and I have encountered a small problem. When reading data back, the MSB of every byte is 0. So, if I write 0xFFFF, I read back 0x7F7F. I have tested line continuity from the Stellaris process, to the D Latch and from there to the SRAM chip. I am using the same parts as the DK-LM3S9B96-FS8. Below is the code I am using to initialize the EPI port, read, and write values. Any advise on what might be going on would be appreciated.
#define EPI_PORTB_PINS (GPIO_PIN_4 | GPIO_PIN_5)#define EPI_PORTC_PINS (GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)#define EPI_PORTD_PINS (GPIO_PIN_2 | GPIO_PIN_3)#define EPI_PORTE_PINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3)#define EPI_PORTF_PINS (GPIO_PIN_4 | GPIO_PIN_5)#define EPI_PORTG_PINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7)#define EPI_PORTH_PINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)#define EPI_PORTJ_PINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6)static volatile unsigned long *sram;void initMemory() { SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ); GPIOPinConfigure(GPIO_PH3_EPI0S0); GPIOPinConfigure(GPIO_PH2_EPI0S1); GPIOPinConfigure(GPIO_PC4_EPI0S2); GPIOPinConfigure(GPIO_PC5_EPI0S3); GPIOPinConfigure(GPIO_PC6_EPI0S4); GPIOPinConfigure(GPIO_PC7_EPI0S5); GPIOPinConfigure(GPIO_PH0_EPI0S6); GPIOPinConfigure(GPIO_PH1_EPI0S7); GPIOPinConfigure(GPIO_PE0_EPI0S8); GPIOPinConfigure(GPIO_PE1_EPI0S9); GPIOPinConfigure(GPIO_PH4_EPI0S10); GPIOPinConfigure(GPIO_PH5_EPI0S11); GPIOPinConfigure(GPIO_PF4_EPI0S12); GPIOPinConfigure(GPIO_PG0_EPI0S13); GPIOPinConfigure(GPIO_PG1_EPI0S14); GPIOPinConfigure(GPIO_PF5_EPI0S15); GPIOPinConfigure(GPIO_PJ0_EPI0S16); GPIOPinConfigure(GPIO_PJ1_EPI0S17); GPIOPinConfigure(GPIO_PJ2_EPI0S18); GPIOPinConfigure(GPIO_PJ3_EPI0S19); GPIOPinConfigure(GPIO_PD2_EPI0S20); GPIOPinConfigure(GPIO_PD3_EPI0S21); GPIOPinConfigure(GPIO_PB5_EPI0S22); GPIOPinConfigure(GPIO_PB4_EPI0S23); GPIOPinConfigure(GPIO_PE2_EPI0S24); GPIOPinConfigure(GPIO_PE3_EPI0S25); GPIOPinConfigure(GPIO_PH6_EPI0S26); GPIOPinConfigure(GPIO_PH7_EPI0S27); GPIOPinConfigure(GPIO_PJ4_EPI0S28); GPIOPinConfigure(GPIO_PJ5_EPI0S29); GPIOPinConfigure(GPIO_PJ6_EPI0S30); GPIOPinConfigure(GPIO_PG7_EPI0S31); GPIOPinTypeEPI(GPIO_PORTB_BASE, EPI_PORTB_PINS); GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS); GPIOPinTypeEPI(GPIO_PORTD_BASE, EPI_PORTD_PINS); GPIOPinTypeEPI(GPIO_PORTE_BASE, EPI_PORTE_PINS); GPIOPinTypeEPI(GPIO_PORTF_BASE, EPI_PORTF_PINS); GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS); GPIOPinTypeEPI(GPIO_PORTH_BASE, EPI_PORTH_PINS); GPIOPinTypeEPI(GPIO_PORTJ_BASE, EPI_PORTJ_PINS); EPIDividerSet(EPI0_BASE, 0); EPIModeSet(EPI0_BASE, EPI_MODE_HB8); EPIConfigHB8Set(EPI0_BASE, (EPI_HB8_MODE_ADMUX | EPI_HB8_WRWAIT_1 | EPI_HB8_RDWAIT_1 | EPI_HB8_WORD_ACCESS), 0); EPIAddressMapSet(EPI0_BASE, (EPI_ADDR_RAM_SIZE_256MB | EPI_ADDR_RAM_BASE_6) ); //EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_16MB | EPI_ADDR_RAM_BASE_6); while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ) { } sram = (unsigned long *)0x68000000;}
int main(void) { unsigned long memoryReadData = 0; SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ); // External 16MHz initMemory(); sram[0] = 0xFFFF; memoryReadData = sram[0];
}
Okay, so it turns out the issue was hardware related and that problem has been resolved.
Now I am attempting to read from flash RAM using the same code (with added fram = (unsigned char *)0x60000000 line, a loop to write incremental values, and another loop to read them back). However, all reads return 0xFF . Any suggestions on what may resolve this issue? Is there anything wrong with the code? Again, same parts and duplicated circuit from DK-LM3S9B96-FS8.
Thanks!
Justin
Justin,
You have referred to the memory device with several different terms. You have called it "flash RAM", "SRAM" and "fram". You have also told us that it is the same parts and circuit as the DK-LM3S9B96-FS8. The FS8 contains both a flash and an SRAM.
If you have properly duplicated the DK-LM3S9B96-FS8 then you should be able to run our example code to verify your circuit. The example code is known to work, don't modify it unless you absolutely have to in order for it to work on your system.
Does your circuit contain both the flash and the SRAM? If so which are you trying to communicate with? I suggest you get the SRAM working first if you have both.
0xFF is the default blank state of most flash memories. Flash often cannot be simply written to like a SRAM it may require special timing and register writes to the device. It also takes a long time to write to and erase flash. If you are immediately reading back what you have written even if the write was done correctly the device may not have completed physically writing the data.
Dexter
Dexter,
I believe I have solved all my issues with the memory. I am using both SRAM and Flash. You are correct that the flash cannot be written to as I would the SRAM, you need to send several bytes to set it to write mode. However, I was unable to find where the read/write operations are used in example code for the kit. Do you know of a specific example?