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TI Home » TI E2E Community » Support Forums » Microcontrollers » Stellaris® ARM® Microcontrollers » Stellaris® ARM® LM3S Microcontrollers Forum » LM3S9B96 (C5) Flash programming issue
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LM3S9B96 (C5) Flash programming issue

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Alexander Chuikov
Posted by Alexander Chuikov
on May 23 2012 10:18 AM
Prodigy60 points

Hello,

I've question relates flash programming for LM3S9B96 (rev. C5XD). Let me explain step-by-step:

  1.  I've a custom board (no external memory and crystal 16MHz) and I create a very simple application which blink LED on E2 (pin 95 for 100-Pin LQFP package). I've been used the "blinky" example from Stellaris library as template (include linker's script)
  2. I use arm-none-eabi GCC based compiler. The compiler works perfectly with LM3S8962, LM3S6965 and some other similar LMxxxx
  3. I use LM3S8962 Evolution Board (Ethernet + CAN) as JTAG to connect host PC with target board (with LM3S9B96)
  4. I use two different kind of flash programming tools but both give same result:
  • OpenOCD 0.5.0 (2011-12-16-08:17) and 0.5.0-dev-00956-ge7269e3 (2012-05-15-00:27) both for Fedora 16x64 (Linux)
  • LM Flasher (Latest version from TI) for Windows 7x64

Result: I can program the chip only one time for LM Flasher or one or two times for OpenOCD. I don't unplug JTAG and power in both case. I could unlock device via LM Flasher but you could understand this is very difficult to debug and test

Could you please help me how to burn flash correctly?

Some additional information:

  1. I've two boards with same chips with same behavior  
  2. I use GCC to build application
  3. I tried to burn uIP example (my custom board has Ethernet like reference) but it doesn't work too
  4. Sorry for my broken English

Best regards,

Alexander

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  • Jonathan Guy
    Posted by Jonathan Guy
    on May 23 2012 10:42 AM
    Expert5700 points

    Hi Alexander,

    This sort of issue is usually due to something in the user code that interfers with subsequent programming operations.  Examples include incorrect clock settings, selecting a clock source that does not exist, and reconfiguring GPIO that are required for the JTAG interface.  Please review your code for any of these conditions.

    Can you program and re-program the blinky binary (unmodified) that comes with StellarisWare?

    Please report the error message provided by the programming tools.  That might provide additional clues.

    Jonathan Guy

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  • Alexander Chuikov
    Posted by Alexander Chuikov
    on May 23 2012 10:59 AM
    Prodigy60 points

    Hi Jonathan,

    Let me add more information about issue.

    The JTAG pins connected to JTAG pins only (directly to MCU)!

    Yes, I've been tried "blinky" (pre-built by keil). The same bad result.

    Best regards,

    Alexander

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  • Jonathan Guy
    Posted by Jonathan Guy
    on May 23 2012 16:01 PM
    Expert5700 points

    A couple of questions:

    When the programming is successful (the first time), does the application run correctly and are you able to see the LED flashing?

    Does the application still run correctly after you attempt to re-program your target board?

     

    Jonathan Guy

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  • Alexander Chuikov
    Posted by Alexander Chuikov
    on May 24 2012 01:42 AM
    Prodigy60 points

    Hi Jonathan,

    I've done some experiments. Summarize:

    1. The "blinky" working correctly (sorry for wrong message in previous post, I missed pin when I checked blinks by scope)
    2. All other examples are failed.
    3. If I add SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |  SYSCTL_XTAL_16MHZ); or other combination for SysCtlClockSet( ... ) I will receive the error: no re-write and application doesn't work.

    So, I've troubles with PLL initialization. I'll try to check (solid another one) crystal and post result.

    Best regards,
    Alexander

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  • Alexander Chuikov
    Posted by Alexander Chuikov
    on May 24 2012 03:03 AM
    Prodigy60 points

    Hi Jonathan,

    Here is the update fore previous post.

    I solid another one crystal (but 8Mhz instead of 16MHz) and it works! I try to solid another 16MHz when I'll find it.

    However I've a few questions relates this topic.

    1. Why broken crystal can block firmware update and "hardware reset" via JTAG? 
    2. Why OpenOCD can not verify the firmware (you could find script below)? 


    #----

    source [find interface/luminary.cfg]
    set WORKAREASIZE 0x4000
    set CHIPNAME lm3s9b9x
    source [find target/stellaris.cfg]

    proc program_device () {
        # halt the processor
        halt
        #wait_halt
        # write file to flash memory
        cortex_m3 maskisr on
        flash write_image erase "./gcc/pnp_eth_can.bin" 0
        verify_image "./gcc/pnp_eth_can.bin"
        cortex_m3 maskisr off
        sleep 10
        #start execution of the program just downladed
        reset run
        sleep 10
        #exit OpenOCD
        shutdown
    }
    init
    reset init
    program_device ()

    #----

    The errors look like:

    Error: checksum mismatch - attempting binary compare
    diff 0 address 0x00000001. Was 0x08 instead of 0x01
    diff 1 address 0x00000004. Was 0x4d instead of 0xe1
    .....

    Could you please help me how to modify script to verify image?

    Best regards,
    Alexander

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  • Jonathan Guy
    Posted by Jonathan Guy
    on May 25 2012 16:28 PM
    Expert5700 points

    Hi Alexander,

    Alexander Chuikov
    • Why broken crystal can block firmware update and "hardware reset" via JTAG? 

    When your code runs, it's selecting and configuring the clock circuit.  If the clock is broken (a static level, or very wrong frequency) the MCU will not function until a power on reset.  The user code runs quickly before the programming tool can intercept the clock configuration. 

    I'm not familiar with OpenOCD, but I will ask others here about your script question.

     

    Jonathan Guy

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  • Alexander Chuikov
    Posted by Alexander Chuikov
    on May 28 2012 15:11 PM
    Prodigy60 points

    Hi Jonathan,

    Thank you for detailed explanation. I'll wait instructions for OpenOCD.

    Best regards,
    Alexander

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  • Jonathan Guy
    Posted by Jonathan Guy
    on May 29 2012 15:11 PM
    Verified Answer
    Verified by Alexander Chuikov
    Expert5700 points

    Alexander,

    I checked with one of our regular openOCD user's and he provided the following information.

    The only additional config items I have in mine are:

    jtag_khz 3000

    jtag_nsrst_delay 100

    reset_config srst_only

    These would go into his script after the second "source" line. The "jtag_khz" probably needs to be lower in order to meet our TCLK <=SYSCLK/8 requirement. Going really slow (like 500) is probably a really good idea in order to just get things working...then bump up the speed to SYSCLK/8 (if it stops working, you know that it is a speed issue and not a connection issue).

    The OpenOCD user mailing list is an excellent resource for assistance with OpenOCD:

     

    http://openocd.sourceforge.net/discussion/mailing-lists/

    Jonathan Guy

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  • Alexander Chuikov
    Posted by Alexander Chuikov
    on May 31 2012 03:41 AM
    Prodigy60 points

    Hi Jonathan,

    Thank you very much!

    Best regards,
    Alexander

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