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JTAG IMPLEMENTATION WITH SPI

Hi all,

I am using LM3S9B96 microcontroller for my project. In My project we implemented JTAG interface with GPIO's and its working fine.  Using this jtag i am able to

transfer 1MB of data in 1 min to ML605. To improve the data rate we are planning to implement JTAG interface with SPI.  Is it possible to implement JTAG with

SPI?. If so how? Please provide me code if any body implemented.

Thanks & Regards,

Mah Kon 

9 Replies

  • I don't have any implementation of this, but do have questions you regarding this concept.

    In your implementation of a JTAG interface using GPIO, how many signals are you controlling?  I presume it is at least 3, ie. TCK, TMS and TDI.  Perhaps you also need TDO for programming the FPGA.  As a master device on the JTAG interface and assuming my assertion is correct regarding the above signals, all 3 signals are outputs of the master device.

    A SPI interface generally has 4 signals, CLK, DI, DO and sometimes CS. I could see a match between TCK and CLK.  I could see a match between DO and TDI.  But what SPI signal would drive TMS?  TMS is an important signal as it is used with TCLK to run the JTAG state machine.

    Currently, I don't see a path to implement this UNLESS you find a device with multiple data output lanes.

  • In reply to BrandonAzbell:

    Pardon - as both speed and signal number are key - should not SWD/SWO be at least a consideration?

  • In reply to cb1_mobile:

    cb1_mobile

    Pardon - as both speed and signal number are key - should not SWD/SWO be at least a consideration?

     
    I made the assumption, perhaps that should teach me something, that the intention of this was to program the FPGA via JTAG by the microcontroller.  I don't spend really any time looking through FPGA documentation, but I'm guessing that SWD/SWO is not an option for the programming interface, rather only JTAG or the exteranl serial flash device for the bitstream.
  • In reply to BrandonAzbell:

    @Brandon-  Agree with you - especially your point re: TMS(how?).   AS SWD is both faster, fewer signaled than JTAG - thought it merited mention...

  • In reply to BrandonAzbell:

    Hi

    I am looking for implementation of JTAG on MSP430 series to program a CPLD. Are you saying that the code is already available?

    Regards,

    Pej

  • In reply to Pejwaak Salimi:

    Don't know whom you're targeting/addressing - but here's my thought.

    In the past - (10+ years) prior to our adoption of, "All ARM - all the time" (thank you God for the newer M0) we bit- banged several Xilinx FPGAs via an 8051/clone MCU.  This appears to be what you seek - so would appear "reasonable" for an ARM - or lesser MSP MCU.

    One of our goals for the use of, "on-board, MCU programming of the FPGA" was the goal of, "Dynamic Reprogrammability" of the FPGA.  (i.e. at different times - based upon program need - certain behaviors of that FPLD would be changed)

    Don't believe that most CPLDs (being simpler) feature that capability. 

    If your development is just starting I'd suggest a more "conventional" CPLD programming method.  KISS - get your system to perform - meet its stated goals first - and only then "attempt" the programming via MCU.

    A visit to the Xilinx site may still contain past tech articles, "care/feeding of MCU-based programming of FPGAs."

  • In reply to cb1-:

    Hi

    Thanks for the reply. My question was about the existence of such firmware/package for MSPs. I don't want to spend so much time implementing this and then realising that the code has been available? Any thoughts on that?

    Regards,

    Pej

  • In reply to Pejwaak Salimi:

    Hi, 

    If such code would existed for MSP, then should ask on MSP forum - here the main processor is Stellaris, core designed by ARM, and could be 100% chance to be different from MSP (although the name/commands must comply with JTAG specifications, internal architecture is quite different).

    Petrei

  • In reply to Pejwaak Salimi:

    Pejwaak Salimi
    I don't want to spend so much time implementing this and then realising that the code has been available?

    Petrei's correct in highlighting your mistargeting - this non-MSP forum.

    Beyond that - any code you may get - if other than vendor generated and/or sanctioned - may not be of highest quality - and most likely was not comprehensively test/verified - under a full slate of operating conditions.  Saving some time (up front) may not yield best/brightest results.  (nor any, "time savings" - when all is said/done!)

    Reference I provided does require that you, "spend requisite time" to gain the recognition of and understanding to produce well considered, proper code.

    [edit] one final point - always wise to provide a, "safety JTAG port" (wired/routed directly to that CPLD) should you encounter issues w/in your MCU implementation - and/or seek faster/easier/direct CPLD programming - w/out burdening your MCU...  (such detail/experience unlikely to result from, "time-saving" as primary objective...)