I keep seeing the following code for setting the clock in some of the example projects:
// // Set the system clock to run at 50MHz from the PLL. // ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ);
How does this set the clock the 50MHz?
If the division is 4 should we not get 16MHz/4 = 4MHz as the clock rate?
You do make sense - but neglect/miss the impact of this function upon the PLL. PLL for many Stellaris can reach 200MHz - thus the divide by 4 yields stated 50MHz. This is covered in the MCU datasheet - may register if you read other than at/around bedtime...
Interesting experiment for you would be to experiment to learn if a "divide by" performs predictably when not running with PLL engaged. (do NOT do this w/ unrecoverable Stellaris or await others to become first victims - protest - should it fail.)
cbi_mobile is right. What that piece of code does is specify that the main oscillator by means of a 16MHz crystal clock will drive the PLL. The PLL produces a 400MHz that is further divided down by 2 (done by hardware) to yield a 200MHz clock signal that is now divided down by the specified SYSCTL_SYSDIV_X value which in our case is 4 and that produces the 50MHz system clock.
I recommend taking a look at the datasheet under the Clock Configuration section to see this.
Moses IsangI recommend taking a look at the datasheet under the...
Indeed - agreed - and nicely detailed. (Such "datasheet look" should not be attempted at/around lights out or -while operating heavy machinery...)
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