I've been staring at the driverlib code in adc.c trying to understand it. It appears that ADCSequenceStepConfigure() ends up referencing registers that aren't documented in the datasheet. Specifically, the function depends on the ADC_O_SSEMUXn offsets from hw_adc.h where n ranges from 0 to 3.
Looking at the #define for ADC_O_SSEMUX0, it's at offset 0x58 from the beginning of the ADC register block. The datasheet (for LM3S9D96), doesn't have anything at this offset. Furthermore, the CMSIS header for the part has a reserved word at that offset.
My assumption is that the four event multiplexer "registers" that appear as a single word per ADC at 0x14 (ACDEMUX) are replicated for each sample sequence and appear at offsets 0x58, 0x78, 0x98 and 0xb8, and that's what ADCSequenceStepConfigure() is using (see line 557 of adc.c). Is that true?
The example code seems to work just fine, so is this just an omission in the datasheet?
The ADCSSEMUXn registers were added for parts that have more than 16 ADC inputs, therefore they are not on the LM3S9D96. If you want to see what they look like, you can find them in the LM4F232 data sheet.
Ah, OK. It might be worth putting a comment in the code to say that some of register writes are no-ops.
Thanks for the prompt response.
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