ADC with Sequencer Interrupt

Hello Abhay,

It looks like you just need to add a IntEnable(INT_ADC0SS3); after your ADCIntEnable() call.

Abhay Kothari

unsigned long Value = 0;

void ADC3IntHandler(void) //INTERRUPT HANDLER
{
//turn on led
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_0, 0x01);
//CLEAR INTERRUPT
ADCIntClear(ADC0_BASE, 3);
//READ DATA
ADCSequenceDataGet(ADC0_BASE, 3, &Value);

}

Be careful here, you'll want to take precautions not to let the compiler optimize 'Value'.  Typically that would be declaring any value used between main code and an interrupt as volatile.  In this case you'll get a compiler warning (gcc anyway) because ADCSequenceDataGet(...) is not prototyped as taking a pointer to a volatile unsigned int.  AFAIK, volatile-ness cannot be cast so you cannot get rid of the warning.  Whether or not the compiler would then feel free to optimize 'Value' inside of ADCSequenceDataGet(...), I am not sure, but I would be wary of it.

You may consider:

volatile unsigned long Value;

void ADC3IntHandler(void)

{

ADCIntClear(ADC0_BASE, 3);

unsigned long temp = 0;

ADCSequenceDataGet(ADC0_BASE, 3, &temp);

Value = temp;

}

Bit of a pile-up this frequency (post) - do agree with TI Mitch about necessity for ADCIntEnable().

Beyond that: your code (below) seems not to meet normal/customary Stellaris MCU spec (framed in yellow) for ADC Operation:

SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ);

With an 8MHz xtal and PLL bypassed - appears that you are in spec violation.  (never a good idea)

Note that you seek example & illustrations (for action) - yet provide neither for we attempting to assist!   (True poetic justice - n'est pas?)  

Your, "Code doesn't work" - doesn't work for we remote diagnosticians either...

Thanks for pointing that out ,but i dont know how to use the PLL,do tell me how to use it . . .when i mean code doesn't work i mean the ADC code 

Thanks Mitch,

That helped :)

Abhay Kothari

dont know how to use the PLL

Almost every example w/in StellarisWare illustrates - also you should focus upon SW-DRL-UG8555 (or newer) which provides just the detail you need.

    ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_25MHZ |
                       SYSCTL_OSC_MAIN);

Note 2nd pararmeter: SYSCTL_USE_PLL - this enables the PLL.  This function divides the 200MHz PLL by 4 - yielding a 50MHz MCU System Clock.  You require a system clock of 16MHz or greater to comply with TI's ADC spec.

Final note: "ADC doesn't work" while marginally improving, "doesn't work" - may itself not win many awards for clarity or detail.  Is it off by 2-3 Lsb when converting, occasionally "slip" a conversion, or never converts at all?   (your readers have no clue!)   Can easily list 10 other "doesn't work" - but continue to "argue strongly against" use of such "information-free" phrase.  (quick, uninspired fault descriptions usually will yield poor response...we know that you can do better...)