LM3S9B96 1-Pin Clock Source

I will need to look up a few things before I can answer this question.  However, which Stellaris device are you using for this application?

--Bobby

Oops, failed to look at the title of the post ... LM3S9B96.  Long day already :-)

--Bobby

Thanks.  Also, the oscillator I am using is the programmable Abracon ASEMB-Blank, which I have programmed at 78 MHz.

According to the data sheet, Section 26.8.1, Table 26-7, the maximum frequency that can be used in this mode is 16.384 MHz..

--Bobby

Please see this post: http://e2e.ti.com/support/microcontrollers/stellaris_arm_cortex-m3_microcontroller/f/471/t/112917.aspx

The datasheet is incorrect on that point.  If my code is wrong for this setup, how should it be corrected?

Thanks!

Also: http://e2e.ti.com/support/microcontrollers/stellaris_arm_cortex-m3_microcontroller/f/471/t/119876.aspx

In specific, I want to use an external oscillator so that I may use that frequency as the base for the CAN interface baud rate, so that I can have better frequency options with our controller module which uses a base of 26 MHz.  What do I need to do now that I have an external oscillator in order to make this happen?

In http://e2e.ti.com/support/microcontrollers/stellaris_arm_cortex-m3_microcontroller/f/471/p/133209/483753.aspx it was determined that the proper way to set up a 50MHz oscillator is with this call: SysCtlClockSet ( SYSCTL_USE_OSC | SYSCTL_OSC_MAIN | SYSCTL_SYSDIV_1);

I have made that change, but I am still having the same issue.  Can I get a confirmation that the circuit I am using is appropriate for the Stellaris?  I was unable to find an example specifically for the Stellaris, so I used one I found for the AM3517.

Update: Swapped out the oscillator for one programmed at 26 MHz and I can now step through the code in the debugger.  However, when I scope the OSC0 pin, the signal is only 1.72 V peak to peak.  Could I get a confirmation that the datasheet is correct with the maximum low voltage on the OSC0 pin is 0.5V and the minimum high (at VDD=3.3) is 2.8V?  It seems like it should not be working right now.

Thanks!

Justin,

Are you using an active probe to measure the voltage?

Regards,

Sue

Sue,

Unfortunately I am only using a passive probe.

Thanks,

Justin

A passive probe will damp the oscillation, so you are not seeing the true amplitude of the signal.

Regards,

Sue

Might not a premium, very fast buffer from TI - interposed between osc_out and poster's scope probe - serve as "poor-man's" active-lite probe?

Okay, then assuming that the oscillator is operating correctly - how do I set this up to work? Is there something extra I need to do for it to work at 78 MHz as opposed to 26 MHz? Again, I am using this line of code:

SysCtlClockSet ( SYSCTL_USE_OSC | SYSCTL_OSC_MAIN | SYSCTL_SYSDIV_1);

Is this correct?

Thanks,

Justin

Hi Justin,

I'm sorry I didn't catch this before.  The maximum frequency for an external clock reference is 50 MHz - see table 26-11 in the data sheet.  Your SysCtlClockSet function is correct.

Regards,

Sue

Thanks Sue. I was looking on an older datasheet where the same table specified 80 MHz. Okay, using 39 MHz I have been able to test that SPI, i2C, and CAN work from the external oscillator. However, I am having trouble using the EPI bus with my SRAM chip. It works fine at 40 MHz PLL, but using the 39 MHz oscillator I get seemingly random data when I read back from SRAM. Is there any modification that I would need to make to the EPI initialization to take into account this different clock source?

My EPI initialization is:

SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);

GPIOPinConfigure(GPIO_PH3_EPI0S0);
GPIOPinConfigure(GPIO_PH2_EPI0S1);
GPIOPinConfigure(GPIO_PC4_EPI0S2);
GPIOPinConfigure(GPIO_PC5_EPI0S3);
GPIOPinConfigure(GPIO_PC6_EPI0S4);
GPIOPinConfigure(GPIO_PC7_EPI0S5);
GPIOPinConfigure(GPIO_PH0_EPI0S6);
GPIOPinConfigure(GPIO_PH1_EPI0S7);
GPIOPinConfigure(GPIO_PE0_EPI0S8);
GPIOPinConfigure(GPIO_PE1_EPI0S9);
GPIOPinConfigure(GPIO_PH4_EPI0S10);
GPIOPinConfigure(GPIO_PH5_EPI0S11);
GPIOPinConfigure(GPIO_PF4_EPI0S12);
GPIOPinConfigure(GPIO_PG0_EPI0S13);
GPIOPinConfigure(GPIO_PG1_EPI0S14);
GPIOPinConfigure(GPIO_PF5_EPI0S15);
GPIOPinConfigure(GPIO_PJ0_EPI0S16);
GPIOPinConfigure(GPIO_PJ1_EPI0S17);
GPIOPinConfigure(GPIO_PJ2_EPI0S18);
GPIOPinConfigure(GPIO_PJ3_EPI0S19);
GPIOPinConfigure(GPIO_PD2_EPI0S20);
GPIOPinConfigure(GPIO_PD3_EPI0S21);
GPIOPinConfigure(GPIO_PB5_EPI0S22);
GPIOPinConfigure(GPIO_PB4_EPI0S23);
GPIOPinConfigure(GPIO_PE2_EPI0S24);
GPIOPinConfigure(GPIO_PE3_EPI0S25);
GPIOPinConfigure(GPIO_PH6_EPI0S26);
GPIOPinConfigure(GPIO_PH7_EPI0S27);
GPIOPinConfigure(GPIO_PJ4_EPI0S28);
GPIOPinConfigure(GPIO_PJ5_EPI0S29);
GPIOPinConfigure(GPIO_PJ6_EPI0S30);
GPIOPinConfigure(GPIO_PG7_EPI0S31);

GPIOPinTypeEPI(GPIO_PORTB_BASE, EPI_PORTB_PINS);
GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS);
GPIOPinTypeEPI(GPIO_PORTD_BASE, EPI_PORTD_PINS);
GPIOPinTypeEPI(GPIO_PORTE_BASE, EPI_PORTE_PINS);
GPIOPinTypeEPI(GPIO_PORTF_BASE, EPI_PORTF_PINS);
GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS);
GPIOPinTypeEPI(GPIO_PORTH_BASE, EPI_PORTH_PINS);
GPIOPinTypeEPI(GPIO_PORTJ_BASE, EPI_PORTJ_PINS);

EPIDividerSet(EPI0_BASE, 0);

EPIModeSet(EPI0_BASE, EPI_MODE_HB8);

EPIConfigHB8Set(EPI0_BASE, (EPI_HB8_MODE_ADMUX | EPI_HB8_WRWAIT_1 |
EPI_HB8_RDWAIT_1 | EPI_HB8_WORD_ACCESS), 0);

EPIAddressMapSet(EPI0_BASE, (EPI_ADDR_RAM_SIZE_256MB |
EPI_ADDR_RAM_BASE_6) );

while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ)

{

}

sram = (unsigned long *)0x68000000;

Thanks!

Justin