The datasheet of LM3S811 says :
Bit rates are supported to 1.5 MHz and higher, although maximum bit rate is determined byperipheral devices.
For master mode, the system clock must be at least two times faster than the SSIClk. Forslave mode, the system clock must be at least 12 times faster than the SSIClk.
that is,
2*SSIClk<=sysclk(Master mode)
12*SSIClk<=sysclk(Slave mode)
While on the PDL-LM3S-UG-3416.pdf:
FSSI >= 2 bit rate (master mode)FSSI >= 12 bit rate (slave modes)
FSSI should be equal to SSIClk. Seemingly there is something wrong with the datasheet.
huangzhechen,
The FSSI is referring to the frequency of the clock supplied to the SSI module.
For example:
If the Stellaris is operating in master mode and the slave provides a clock of 10kHz, then the internal clock of the SSI peripheral on the Stellaris (FSSI) needs to be:
FSSI >= 2 bit rate
in this case FSSI >= 2 * (10kHz)
Therefore the SSI peripheral must have an internal clock of at least 20kHz. Make sense?
Also the document you are referring to (PDL-LM3S-UG-3416.pdf) is outdated. Please refer to the DriverLib doc that installed with StellarisWare.
"<StellarisWare install directory>\docs\ SW-DRL-UG-xxxx.pdf"
-Dave