hi,
i need to use EPI bus in HB16 mode for LM3S2B93 but EPIConfigHB16set() function is not available in epi.c and epi.h file provided with stellarisware.
. can anybody help me for the definition of this function or updated stellarisware having functions related to EPI bus in HB16 mode.
This function is defined in the latest version of StellarisWare. Which version are you using?
Current version is 9107 available at http://www.ti.com/tool/sw-lm3s
You should also be able to determine the proper register settings by looking at the datasheet and the HB8 version of the function.
Dexter
Thanks Dexter,
Previously i was using Stellarisware version 5228 and EPIConfigHB16Set () function was not given there , now i have installed latest version 9107 as you suggested and i got the definition and declaration of all function and constant associated with HB16 mode of EPI. but when i build and run my project this will go to fault ISR . if u can done one favor for me then please check my code i copy this below. and tell me whether something is missing there#include "inc/lm3s2b93.h"#include "inc/hw_types.h"#include "driverlib/epi.h"#include "inc/hw_memmap.h"#include "inc/hw_gpio.h"#include "driverlib/gpio.h"#include "inc/hw_epi.h"#include "driverlib/sysctl.h"#include "driverlib/debug.h"#define START_ADDRESS 0xA0000000void EPI_W_FPGA(unsigned short * w_addr, unsigned short w_data){ * w_addr = w_data; }unsigned short EPI_R_FPGA(unsigned short * w_addr){ return (*w_addr);}intmain(void){ unsigned short *ptr=(unsigned short *)START_ADDRESS; unsigned short byte=0,byte_array[16]={0,}; unsigned short idata=0x5555; SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN |SYSCTL_XTAL_12MHZ); // Set Frequency 12 MHz SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0); // enable EPI SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); // enable port B SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); // enable port C SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); // enable port D SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE); // enable port E SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); // enable port F SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG); // enable port G SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH); // enable port H SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ); // enable port J GPIOPinConfigure(GPIO_PH3_EPI0S0); //pin config EPI0 GPIOPinConfigure(GPIO_PH2_EPI0S1); GPIOPinConfigure(GPIO_PC4_EPI0S2); GPIOPinConfigure(GPIO_PC5_EPI0S3); GPIOPinConfigure(GPIO_PC6_EPI0S4); GPIOPinConfigure(GPIO_PC7_EPI0S5); GPIOPinConfigure(GPIO_PH0_EPI0S6); GPIOPinConfigure(GPIO_PH1_EPI0S7); GPIOPinConfigure(GPIO_PE0_EPI0S8); GPIOPinConfigure(GPIO_PE1_EPI0S9); GPIOPinConfigure(GPIO_PH4_EPI0S10); GPIOPinConfigure(GPIO_PH5_EPI0S11); GPIOPinConfigure(GPIO_PF7_EPI0S12); GPIOPinConfigure(GPIO_PG0_EPI0S13); GPIOPinConfigure(GPIO_PG1_EPI0S14); GPIOPinConfigure(GPIO_PG4_EPI0S15); GPIOPinConfigure(GPIO_PJ0_EPI0S16); GPIOPinConfigure(GPIO_PJ1_EPI0S17); GPIOPinConfigure(GPIO_PJ2_EPI0S18); GPIOPinConfigure(GPIO_PD4_EPI0S19); GPIOPinConfigure(GPIO_PD2_EPI0S20); GPIOPinConfigure(GPIO_PD3_EPI0S21); GPIOPinConfigure(GPIO_PB5_EPI0S22); GPIOPinConfigure(GPIO_PB4_EPI0S23); GPIOPinConfigure(GPIO_PE2_EPI0S24); GPIOPinConfigure(GPIO_PE3_EPI0S25); GPIOPinConfigure(GPIO_PH6_EPI0S26); GPIOPinConfigure(GPIO_PH7_EPI0S27); GPIOPinConfigure(GPIO_PD5_EPI0S28); GPIOPinConfigure(GPIO_PD6_EPI0S29); GPIOPinConfigure(GPIO_PD7_EPI0S30); GPIOPinConfigure(GPIO_PG7_EPI0S31); GPIOPinTypeEPI(GPIO_PORTH_BASE,GPIO_PIN_3 ); //AD0 GPIOPinTypeEPI(GPIO_PORTH_BASE,GPIO_PIN_2 ); //AD1 GPIOPinTypeEPI(GPIO_PORTC_BASE,GPIO_PIN_4 ); //AD2 GPIOPinTypeEPI(GPIO_PORTC_BASE,GPIO_PIN_5 ); //AD3 GPIOPinTypeEPI(GPIO_PORTC_BASE,GPIO_PIN_6 ); //AD4 GPIOPinTypeEPI(GPIO_PORTC_BASE,GPIO_PIN_7 ); //AD5 GPIOPinTypeEPI(GPIO_PORTH_BASE,GPIO_PIN_0 ); //AD6 GPIOPinTypeEPI(GPIO_PORTH_BASE,GPIO_PIN_1 ); //AD7 GPIOPinTypeEPI(GPIO_PORTE_BASE,GPIO_PIN_0 ); //AD8 GPIOPinTypeEPI(GPIO_PORTE_BASE,GPIO_PIN_1 ); //AD9 GPIOPinTypeEPI(GPIO_PORTH_BASE,GPIO_PIN_4 ); //AD10 GPIOPinTypeEPI(GPIO_PORTH_BASE,GPIO_PIN_5 ); //AD11 GPIOPinTypeEPI(GPIO_PORTF_BASE,GPIO_PIN_7 ); //AD12 GPIOPinTypeEPI(GPIO_PORTG_BASE,GPIO_PIN_0 ); //AD13 GPIOPinTypeEPI(GPIO_PORTG_BASE,GPIO_PIN_1 ); //AD14 GPIOPinTypeEPI(GPIO_PORTG_BASE,GPIO_PIN_4 ); //AD15 GPIOPinTypeEPI(GPIO_PORTJ_BASE,GPIO_PIN_0 ); //A16 GPIOPinTypeEPI(GPIO_PORTJ_BASE,GPIO_PIN_1 ); //A17 GPIOPinTypeEPI(GPIO_PORTJ_BASE,GPIO_PIN_2 ); //A18 GPIOPinTypeEPI(GPIO_PORTD_BASE,GPIO_PIN_4 ); //A17 GPIOPinTypeEPI(GPIO_PORTD_BASE,GPIO_PIN_2 ); //A18 GPIOPinTypeEPI(GPIO_PORTD_BASE,GPIO_PIN_3 ); //A19 GPIOPinTypeEPI(GPIO_PORTB_BASE,GPIO_PIN_5 ); //A20 GPIOPinTypeEPI(GPIO_PORTB_BASE,GPIO_PIN_4 ); //A21 GPIOPinTypeEPI(GPIO_PORTE_BASE,GPIO_PIN_2 ); //A22 GPIOPinTypeEPI(GPIO_PORTE_BASE,GPIO_PIN_3 ); //A23 GPIOPinTypeEPI(GPIO_PORTH_BASE,GPIO_PIN_6 ); //EPI_CS0 GPIOPinTypeEPI(GPIO_PORTH_BASE,GPIO_PIN_7 ); //EPI_CS0 GPIOPinTypeEPI(GPIO_PORTD_BASE,GPIO_PIN_5 ); //EPI_RD GPIOPinTypeEPI(GPIO_PORTD_BASE,GPIO_PIN_6 ); //EPI_WR GPIOPinTypeEPI(GPIO_PORTD_BASE,GPIO_PIN_7 ); //EPI_ALE GPIOPinTypeEPI(GPIO_PORTG_BASE,GPIO_PIN_7 ); //EPI_clk GPIOPinTypeEPI(GPIO_PORTE_BASE,GPIO_PIN_2 ); //EPI_BLE GPIOPinTypeEPI(GPIO_PORTE_BASE,GPIO_PIN_3 ); //EPI_BHE EPIModeSet(EPI0_BASE,EPI_MODE_HB16); // Set Mode As General Purpose /*Address Size 12 bit , Data Size 16 , Clock out on pin , Enable Read Write, Use frame Pin , Enable Read 2 Cycle*/ EPIConfigHB16Set(EPI0_BASE,(EPI_HB16_MODE_ADMUX|EPI_HB16_WRWAIT_2 |EPI_HB16_RDWAIT_2 |EPI_HB16_CSCFG_ALE_DUAL_CS|EPI_HB16_WRHIGH | EPI_HB16_RDHIGH ),0); EPIDividerSet(EPI0_BASE, 0); // clock 12 Mhz EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_16MB | EPI_ADDR_RAM_BASE_6); // Map @ 0xA0000000 of 256 Byte for(byte=0;byte<16;byte++) { EPI_W_FPGA(ptr+byte,idata);//Write 16 bytes idata = (~idata); } for(byte=0;byte<16;byte++) byte_array[byte]=EPI_R_FPGA(ptr+byte);//Read 16 Bytes while(1);}
Nitin Verma
hi ,
Last assembly instruction executes successfully is
EB080042 ADD.W R0, R8, R2, LSL #1
and when try to execute below instruction code will goes under control of Fault ISR()
0x0000036E: F000FBA1 BL EPI_W_FPGA
and status of
NVIC_FAULT_STAT register : either 00000400 or 00001400
NVIC_HFAULT_STAT register: 40000000
NVIC_INT_CTLRL register: 00000803
Based on this information my first guess would be stack corruption or stack overflow. The NVIC_FAULT_STAT Looking at the datasheet bit descriptions you find that 0x400 bit means this is an imprecise error. That means the processor can not say for certain exactly where it occurred or what memory was being accessed that caused the fault. However clues are often still on the stack that can tell you much of that information. The 0x1000 bit tells us this is a stacking error.
We have recently published a good application note on debugging faults.http://www.ti.com/lit/an/spma043/spma043.pdf I believe ARM/Keil also has some similar information in one of their application notes as well as Joseph Yiu's Book "Definitive Guide to the ARM Cortex M3"
In addition to those resources: Try some standard stack debug tricks. Double the size of the stack see if the problem goes away, changes or changes location, these are indications it was stack related. Also most compilers have a way to fill the stack with a known constant during startup (prior to main) or this can be done in the debug memory window manually. Once you have stack filled with a known value you can examine the stack after a failure to see how deep the stack went at the deepest point prior to the failure. You can also see if something else corrupted the stack if random occasional values in the stack region were changed.
HI dexter,
thanks for your reply.
That issue was not related to stack corruption or overflow, but this was related to the start address which i defined initially . that address was not correct for the memory to which i wanted to interface through EPI bus.Start address range for external peripheral and memory for my design was START_ADDRESS 0x68000000 to 0x688FFFFF while i define start address by 0x68A00000.
but your support might be helpful to me in future .
Thanks and Regard
Nitin verma
:)