ADC clock variation

Looking at Table 20-9 (LM3S811 Data Sheet p. 391), I
notice that the ADC clock speed (fADC) and thus the
ADC conversion rate (fADCCONV) can vary +/-12% from
nominal.

Is this simply a reflection of the fact that one Could
drive the ADC clock (via the PLL) using the internal
oscillator (which itself has a rather wide range)? Or
is this really an artifact of the ADC itself?

Would it be reasonable to suppose that, if the PLL were
being driven by an external crystal (as seen on the
EK), the ADC clock/conversion rate would be
arbitrarily close to nominal?

My interest is that I'm looking at a design which would
run the ADC pretty much at maximum speed, and -12%
in the speed could make a difference.

2 Replies

  • There are is something that I need to clear up for you in regards to the operation of the ADC.

    The ADC MUST have a 16MHz reference clock for it to operate correctly, meaning that you must use the PLL (with one of the supported external crystal options) or a 16MHz external clock. Whenever the PLL is enabled, the ADC is supplied with a 16MHz clock signal (with very little error). Essentially, the only variation the ADC will see is whatever variation there is in the PLL (or 16MHz external clock source).

    The 8MHz number is derived from the fact that the ADC on the 811 runs at 500KSps, so the 16MHz is divided one additional time to generate 8MHz.

    Bottom line - you will not see variation on the order of +/- 12%.
  • Thanks for the reassurance.

    I'm still curious though: If the ADC really won't
    function with a "sloppy" clock, why does the Data
    Sheet specify such a huge range? I'm not (now)
    worried, but it is a bit disconcerting.

    Gratuitous flattery: Putting FIFOs on the ADC was a
    Great Idea.