Can anybody confirm what the max spi clock speed this device can support is, I was working under the assumption it was set by the external device and the MCU clock, having seen comments like SPIcan opperate at upto 1/2 MCU frequency so for 50MHz clock --> 25MHz on the SPI.
However, i don't seem to be getting near these rates and i also keep coming across comment in TI/Luminary like in the code samples
// Configure and enable the SSI port for master mode.
// Operate at 4.17MHz - the fastest rate LM3S8xx devices can support
does this device have a ceiling?
Thanks and Best regards
What does the Datasheet say?
What Andy is referrring to is that there are really 2 answers to the maximum clock rate of the SPI interface on the LM3S2948. This is dependent on whether the LM3S2948 is the master on the SPI bus, or a slave on the SPI bus. This is documented in the datasheet in the Synchronous Serial Interface (SSI) Chapter and specifically mentioned in Section 13.2.1 entitled Bit Rate Generation.
Based on your post, I would infer in your use case the LM3S2948 is a slave on the SPI bus. Therefore, as indicated the aforementioned section of the datasheet, the maximum SPI clock rate is equal to the System Clock / 12. In this case, if you are operating the system clock at 50MHz, the maximum SPI clock in slave mode is 50MHz/12, or 4.17MHz.
For reference, when the LM3S2948 is the SPI master, the maximum SPI clock rate is equal to the System Clock / 2, or 25MHz.
Thanks for the feedback. I had read the data sheet ok about the speed being SysClock/2 when the LM3S2948 is the SPI master, the transfer rates we are getting seem slow in comparison to another device we are using, one of the team feedback that that the speed could not be set above 12.5MHz.
Hence I started out myself to get some background on this checked the eratta etc. The started coming across the comments
comment in TI/Luminary like in the code samples
// Configure and enable the SSI port for master mode // Operate at 4.17MHz - the fastest rate LM3S8xx devices can support
So was really just after some confirmation that I had not missed something and the device does support 25MHz operation in master mode, looks like time to get the scope out.
Before finding this forum thread, I did the equivalent calculation for the LM4F111B2QR. My procedure for calculating the results was the same.
TI Stellaris Blizzard LM4F111B2QR Rev A3 SPI max data rate is 13.3 Mbps
Here is the supporting documentation.
Master mode System clock must be 2 times faster than SSIClk used for SPISlave mode System clock must be 6 times faster than SSIClk used for SPISo, worst case SSIClk can be as fast as SysClk/6Max SysClk = 80 MHz (LM4F111B2QR Rev A3)Therefore SSIClk can be as fast as 80 MHz/6 = 13.3 MHz
Stellaris LM4F111B2QR Microcontroller Data Sheet (Rev. A) (PDF 5738 KB) 19 Dec 2011Page 210 of 1117Page 1070 of 1117Page 1072 of 1117Page 885 of 1117
LM3S1W16Electrical Characteristics - Synchronous Serial Interface (SSI)"In master mode, the system clock must be at least twice as fast as the SSIClk; in slave mode, the system clock must be at least 12 times faster than the SSIClk."
Max SysClk = 50 MHz
Master mode SSIClk can be up to 50 Mhz/2 = 25 MHzSlave mode SSIClk can be up to 50 MHz/12 = 4.17 MHz
Therefore the maximum SSIClk for use as both master and slave is 4.17 MHz.
LM3S5T36Electrical Characteristics - Synchronous Serial Interface (SSI)"In master mode, the system clock must be at least twice as fast as the SSIClk; in slave mode, the system clock must be at least 12 times faster than the SSIClk."Max SysClk = 80 MHz
Master mode SSIClk can be up to 80 MHz/4 = 20 MHz (25 MHz would be possible for SysClk = 50 MHz)Slave mode SSIClk can be up to 80 MHz/12 = 6.67 MHz
Therefore the maximum SSIClk for use as both master and slave is 6.67 MHz.
Reference: Data sheet - Synchronous Serial Interface (SSI) --> Functional Description --> Bit Rate Generation
This reporter suspects that this - somewhat unexpected SSIClk speed issue - deserves "promotion" beyond the cheap seats (buried w/in data @ very rear of Manual) to bold-face emphasis very early w/in the SSI Data Chapter.
Certainly this spec belongs within the MCU detailed electrical/operational listings - as is now done - but additional "high-lighting" of the unusual saves user-clients time/money/effort. Getting your users more quickly/efficiently to market translates directly to your bottom line! (and even "unwelcome data" - such as this - will be "softened" when more openly conveyed...)
The information is featured early in the SSI chapter - in section X.3.1 and highlighted as a "Note."
I definitely remember errata that says Stellaris SPI cannot be above 25mhz. So 80/2=40mhz but min(40,25)=25. Furthermore in my testing it appears stellaris cannot run at uneven clock so 80mhz cannot operate 25mhz clock because 80 mhz doesn't divide 25mhz so the fastest you can go is 20mhz with 80mhz clock. Correct me if I am wrong.
There is no erratum associated with the maximum SSI speed, but you are correct that there is a limit of 25 MHz which is detailed in the data sheet. You are also correct that you must divide the system clock by an even integer, so 20 MHz is the fastest you can go with an 80 MHz clock.
Thanks Henry and Sue. I stand corrected. I've fixed the mistake by editing my previous post.
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