SPI max clock speed on LM3S2948

What does the Datasheet say?

Hi Brandon,

Thanks for the feedback. I had read the data sheet ok about the speed being SysClock/2 when the LM3S2948 is the SPI master, the transfer rates we are getting seem slow in comparison to another device we are using, one of the team feedback that that the speed could not be set above 12.5MHz. 

Hence I started out myself to get some background on this checked the eratta etc. The started coming across the comments

comment in TI/Luminary like in the code samples

 // Configure and enable the SSI port for master mode
 // Operate at 4.17MHz - the fastest rate LM3S8xx devices can support

So was really just after some confirmation that I had not missed something and the device does support 25MHz operation in master mode, looks like time to get the scope out.

Best regards

Darren

Before finding this forum thread, I did the equivalent calculation for the LM4F111B2QR.  My procedure for calculating the results was the same.

TI Stellaris Blizzard LM4F111B2QR Rev A3 SPI max data rate is 13.3 Mbps

Here is the supporting documentation.

Master mode
    System clock must be 2 times faster than SSIClk used for SPI
Slave mode
    System clock must be 6 times faster than SSIClk used for SPI
So, worst case SSIClk can be as fast as SysClk/6
Max SysClk = 80 MHz (LM4F111B2QR Rev A3)
Therefore SSIClk can be as fast as 80 MHz/6 = 13.3 MHz

Stellaris LM4F111B2QR Microcontroller Data Sheet (Rev. A)  (PDF 5738 KB)  19 Dec 2011
Page 210 of 1117
Page 1070 of 1117
Page 1072 of 1117
Page 885 of 1117

LM3S1W16
Electrical Characteristics - Synchronous Serial Interface (SSI)
"In master mode, the system clock must be at least twice as fast as the SSIClk; in slave mode, the system clock must be at least 12 times faster than the SSIClk."

Max SysClk = 50 MHz

Master mode
  SSIClk can be up to 50 Mhz/2 = 25 MHz
Slave mode
  SSIClk can be up to 50 MHz/12 = 4.17 MHz

Therefore the maximum SSIClk for use as both master and slave is 4.17 MHz.

LM3S5T36
Electrical Characteristics - Synchronous Serial Interface (SSI)
"In master mode, the system clock must be at least twice as fast as the SSIClk; in slave mode, the system clock must be at least 12 times faster than the SSIClk."
Max SysClk = 80 MHz

Master mode
  SSIClk can be up to 80 MHz/4 = 20 MHz (25 MHz would be possible for SysClk = 50 MHz)
Slave mode
  SSIClk can be up to 80 MHz/12 = 6.67 MHz

Therefore the maximum SSIClk for use as both master and slave is 6.67 MHz.

Reference: Data sheet - Synchronous Serial Interface (SSI) --> Functional Description --> Bit Rate Generation

This reporter suspects that this - somewhat unexpected SSIClk speed issue - deserves "promotion" beyond the cheap seats (buried w/in data @ very rear of Manual) to bold-face emphasis very early w/in the SSI Data Chapter. 

Certainly this spec belongs within the MCU detailed electrical/operational listings - as is now done - but additional "high-lighting" of the unusual saves user-clients time/money/effort.  Getting your users more quickly/efficiently to market translates directly to your bottom line!   (and even "unwelcome data" - such as this - will be "softened" when more openly conveyed...)

Hi cb1,

The information is featured early in the SSI chapter - in section X.3.1 and highlighted as a "Note."

Regards,

Sue

I definitely remember errata that says Stellaris SPI cannot be above 25mhz.  So 80/2=40mhz but min(40,25)=25.  Furthermore in my testing it appears stellaris cannot run at uneven clock so 80mhz cannot operate 25mhz clock because 80 mhz doesn't divide 25mhz so the fastest you can go is 20mhz with 80mhz clock.  Correct me if I am wrong.

Thanks Henry and Sue.  I stand corrected.  I've fixed the mistake by editing my previous post.