Stellaris® ARM® Microcontrollers

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Stellaris® ARM® Microcontrollers

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LM3S2B93
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  • Forum Post: 16 Bit Atomic Write for LM3S2B93

    Abu Saajeedullah
    Hi Everyone, I am working with the LM3S2B93 Microcontroller. I am trying to put a 16 bit value to the outside world. These 16 bit value will be used as dicrete output for different peripherals. To do so I am trying to use 2 GPIO Ports (8 bit each) as one 16 Bit GPIO port. So I was wondering is it...
    on Sep 21, 2010

  • Forum Post: Recovering from CAN Bus Errors

    Allen Moore
    I'm working with a multi-board, CAN-connected system using LM3S9B92, LM3S2B93, and LM3S2793 parts with the Stellaris Peripheral Driver Library. I need to write error-handling code for all the different conditions reported by the CAN Status register (BOFF, EWARN, EPASS, and the LEC codes). However...
    on Oct 7, 2010

  • Forum Post: Programming Issues with Rev C1/C3 of LM3S9B92 & LM3S2B93

    Allen Moore
    We have a four-board (custom) system using LM3S9B92 and LM3S2B93 parts. We started with revision B1 silicon and life was good. No problem programming with Keil's uVision 4.10 (RealView MDK-ARM toolchain 4.12) or with the LM Flash Programmer utility (build 1154). We made a new set of boards to fix...
    on Oct 18, 2010

  • Forum Post: Stellaris LM3S2B93 2B93 Is clearing GPIODEN sufficient to tri-state device pins? mrne2epost

    Newman
    Hello, My customer would like to know if clearing the appropriate bit in the GPIODEN register is sufficient to disconnect input buffers on a pin so that the pin can float (essentially tristate). According to the datasheet… “On reset, all GPIO pins are configured to be undriven (tristate...
    on Dec 21, 2010

  • Forum Post: Re: Strange I2C behavior

    Nathan Goslee
    Hi Alex, Regarding the BUSY during ISR, it appears that when a I2C_MASTER_CMD_BURST_SEND_START fails, it raises the interrupt before the I2C master finishes the operation (perhaps due to ADRACK being set before the data transfer completes?). I also observed that the I2C_MASTER_CMD_BURST_SEND_ERROR_STOP...
    on Sep 1, 2011

  • Forum Post: Troubleshooting LM3S2B93 to discover BOOTCFG register had been accidentally set to undesired configuration

    Jason Work
    customer We are having a problem with TI part LM3S2B93 C5 received from [our distributor] at [our contract manufacturer] in China where manufacturing of our product is happening. We need your help to troubleshoot this problem. Out of the 200 boards they built, 3/4 of them are failing. We are still...
    on Jan 13, 2012

  • Forum Post: RE: LM3S2B93 Hibernation Module

    Erick Macias
    Hello David, The LM3S2B93 IQC80 C5 SD will have the "Write to certain hibernation modules register sometimes fail" errata. Have you tried the workaround provided in the Errata ? The data sheet provides the steps required to initialize the hibernate RTC (no hibernation) in page 303. RTC...
    on May 8, 2012

  • Forum Post: LM3S2B93 Hibernation Module

    David Escandon
    TI Team, Can you confirm whether or not the LM3S3B93 has a faulty Hibernation module? The errata indicates that writing to certain hibernation registers will fail due to a system clocking issue. (see link below) It also states the the silicon version that is affected is "C5." Below are the...
    on May 8, 2012

  • Forum Post: Using SSI0 with uDMA

    Matthew Fratkin
    I am having some issues getting the uDMA and SSI0 to work on the LM3S2B93. I have been able to get just SSI0 working as well as the UART0 with uDMA but when I attempt to make SSI0 transfers using the uDMA I keep getting errors in my uDMAErrorHandler ISR. I have seen a couple of examples of how to set...
    on Jun 12, 2012

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