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Debug Port Unlock on Uniflash 3.1 (and error message)

Other Parts Discussed in Thread: UNIFLASH, LMFLASHPROGRAMMER

Hello all.

We have one doubt regarding this feature on the latest Uniflash release.

Is it possible to Unlock a 129X Tiva device with a XDS100 v2? We can erase the flash with this JTAG device, program the chip and read and write the registers (so the connections are OK), but after a Debug Unlock port, the chip stays the same.

We have tried connecting the TRST port of the JTAG to  the RST pint of the 129 microcontroller as well with the same results.

We can unlock it in uniflash with a ICDI stellaris board.

On the other hand, I also receive this message many times:

Everytime I get the message, we need to exit Uniflash and reset the JTAG board to get it working again.

Why is that? Is it a know bug?

  • Hello PAk,

    When you mention "the chip stays the same" do you mean the Flash does not get erased?

    I know some folks have used UniFlash with XDS100 emulators to do so and they haven't faced an issue like seen in the snapshot

    http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/p/327027/1138657.aspx#1138657

    Regards

    Amit

  • Amit Ashara said:
    When you mention "the chip stays the same" do you mean the Flash does not get erased?

    Thank you Amit, with that I mean that the flash doesn't get erased, the use registers keep their value and the program is not erased (so no unlock) and starts running again after a Debug Unlock Port.

    If I send an Erase Flash command, the flash is erased completely.

    Amit Ashara said:

    I know some folks have used UniFlash with XDS100 emulators to do so and they haven't faced an issue like seen in the snapshot

    http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/p/327027/1138657.aspx#1138657

    I hace tried the same connections than these folks, and I am having the same results, no flashing with debug unlock and xds100 v2 (everything Works with a launchpad as expected)

    How can I debug this issue?

    Thank you

  • Hello PAk,

    The JTAG Unlock mechanism requires that the user power up the board with the reset button pressed, then run the unlock sequence, release the reset and then power cycle the board. Was this the procedure?

    Regards

    Amit

  • Amit Ashara said:

    The JTAG Unlock mechanism requires that the user power up the board with the reset button pressed, then run the unlock sequence, release the reset and then power cycle the board. Was this the procedure?

    Of course, as I told before, we were able to unlock the chip via an ICDI Stellaris device.

    It is worth saying, that we have tried on another computer with the same result and messages of error. We are using a Spectrum Digital xds100 v2 Rev c. JTAG device.

    Could you provide us with a procedure to debug this issue?

    Thank you Amit.

  • Hello PAk,

    Is this a DK-TM4C129X or EK-TM4C129X that you are using? I will have to try the same so want to make sure that the right board is being used.

    Regards

    Amit

  • Amit Ashara said:

    Is this a DK-TM4C129X or EK-TM4C129X that you are using? I will have to try the same so want to make sure that the right board is being used.

    Actually I am using a custom board with a XM4C129-ENCPDT and EK-TM4C129X.

    It seems to be a problem with the JTAG it self, since the error message appears even with the JTAG not connected to the board.

    Regards

  • Hello PAk,

    So a basic JTAG connection to the custom board is not happening, is that correct? Can you send the schematics of the JTAG header on the board. Please note that XDS100V2 is some of the past E2E threads here does not work if some of the pins like TDIS and Vref are not connected.

    Regards

    Amit

  • Amit Ashara said:
    So a basic JTAG connection to the custom board is not happening, is that correct?

    I am afraid you are wrong. Please read again the first post of this thread, where I say:

    PAk said:

    Is it possible to Unlock a 129X Tiva device with a XDS100 v2? We can erase the flash with this JTAG device, program the chip and read and write the registers (so the connections are OK), but after a Debug Unlock port, the chip stays the same.

    We have tried connecting the TRST port of the JTAG to  the RST pint of the 129 microcontroller as well with the same results.

    Basically, this is what I can do with both our programmers:

    Stellaris ICDI XDS100v2
    Program YES YES
    Read Registers YES YES
    Erase Flash YES YES
    Debug Unlock Port YES NO

    So, the question is why we cannot Unlock the chip with XDS100.

    Of course we have the TDIS pin (4) to ground.

    We have tried, as well, to connect the RST pin of the JTAG to the reset pin of the chip with no luck.

    Thank you

  • Hello PAk,

    My fault. Was misdirected by

    --------------

    It seems to be a problem with the JTAG it self, since the error message appears even with the JTAG not connected to the board.

    --------------

    I see that Uniflash v3.1 has been released after the last post. I would need to check with the debugger team as to is the XDS100V2 support for this application been deprecated!!! If yes, then it is a serious issue for us...

    Regards

    Amit

  • Thank you Amit.

    We have tried with two different XDS100 v2 JTAG devices in two different computers with Uniflash 3.1 with the same result.

    On the other hand, I would like to thank you publicly for your support, effort and diligence answering most of the questions on this forum. From my point of view, the support today is being very good.

    We wait to your answer to proceed.

    Regards.

  • Hi Amit.

    Could you tell us something regarding this issue with XDS100 and Uniflash 3.1 ?

    Thank you

  • Hello PAk,

    My apologies, I couldn't make some time to work on this and the UNIFLASH Team is also checking. Hopefully I should be able to put out some results tomorrow.

    Regards

    Amit

  • Hello PAk,

    I checked with UNIFLASH Team and XDS100V2 is not supported for Debug Unlock Feature.

    Regards

    Amit

  • Amit Ashara said:

    Hello PAk,

    I checked with UNIFLASH Team and XDS100V2 is not supported for Debug Unlock Feature.

    Regards

    Amit

    Thank you Amit.

    Do you know if it will be supported in the future?

    We are providing some libraries on our custom made boards to some of our customers, but they are writing/extending their own software...give them a TIVA Launchpad board for unlocking their devices does not seem very professional to us.

    Is there any other recommended way? We are talking about bussiness here.

    Regards

  • Hello PAk,

    I can check that for you if XDS100V2 is going to be supported. I would be cautious though as getting different debuggers to do something custom like Unlock for TIVA may take time.

    Regards,

    Amit

  • Amit Ashara said:

    Hello PAk,

    I can check that for you if XDS100V2 is going to be supported. I would be cautious though as getting different debuggers to do something custom like Unlock for TIVA may take time.

    Regards,

    Amit

    Thank you Amit.

    That would be at least helpful, to know what to expect and when to expect it.

    There was somebody in this forum who implemented this unlock procedure on an ATMEL uC, so it i almost there.

    http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/297875.aspx

    Regards

  • Hello PAk,

    For that matter if using another uC, you can do that with another TIVA Processor also, along with controlling the Power and Reset to the main TIVA. But having it as part of the debug environment would always be an add-on.

    Regards

    Amit

  • Hello PAk,

    Amit Ashara said:

    I can check that for you if XDS100V2 is going to be supported. I would be cautious though as getting different debuggers to do something custom like Unlock for TIVA may take time.

    Regards,

    Amit

    Hello Amit.

    Do you have the answer for this?

    Amit Ashara said:

    Hello PAk,

    For that matter if using another uC, you can do that with another TIVA Processor also, along with controlling the Power and Reset to the main TIVA. But having it as part of the debug environment would always be an add-on.

    Regards

    Amit

    From my point of view, this is something TI may provide. 
    As I told before, it does not look professional to provide a Stellaris / Tiva Launchpad to our clients for unlocking/debugging. Actually, I don't like the idea of one board, unlocking the other, I think XDS100 unlocking capability is the way to go.....
    Regards
  • Hello PAk,

    They are evaluating if the XDS100 gives the capability to run bare JTAG Sequences as TIVA uses JTAG-TO-SWD and SWD-TO-JTAG switching sequences which XDS100 does not supprt.

    I don't expect an answer soon either as they have multiple products to support and they indicated that it is the feature of LMFlashProgrammer that has been imported as is into UNIFLASH

    Regards

    Amit

  • Amit Ashara said:

    Hello PAk,

    They are evaluating if the XDS100 gives the capability to run bare JTAG Sequences as TIVA uses JTAG-TO-SWD and SWD-TO-JTAG switching sequences which XDS100 does not supprt.

    I don't expect an answer soon either as they have multiple products to support and they indicated that it is the feature of LMFlashProgrammer that has been imported as is into UNIFLASH

    Regards

    Amit

    Thank you Amit for your quick answer.

    Then why not release/post the code  for Tiva that unlocks any other Tiva/Stellaris chip? TI has it implemented as part/function of the ICDI firmware, so it is not a great effort from your resources, but a big help for us, developers and community.

    Regards.

  • Hello PAk,

    While I try to find a reasonable workaround or resolution, if you plan to put another TIVA, then you can implement a JTAG Unlock Sequence on the second TIVA which can work w/o the user pressing reset while powering up.

    I have actually done this using two TIVA parts.

    Regards

    Amit

  • Amit Ashara said:

    Hello PAk,

    While I try to find a reasonable workaround or resolution, if you plan to put another TIVA, then you can implement a JTAG Unlock Sequence on the second TIVA which can work w/o the user pressing reset while powering up.

    I have actually done this using two TIVA parts.

    Regards

    Amit

    Thank you Amit you are very helpful. 

    For the moment, we down't know hot to perform the unlock procedure contrlling the power and reset of the second ic.

    Would you mind to post a snippet of code?

    Thank you again.

  • Hello PAk

    Attached is the code sequence that I run on a TM4C129X with System Clock of 16MHz. This sequence is extracted from my main program, but I have tried to encapsulate the functions

    Regards

    Amit

    3806.uCUnlock.c
    uint32_t ui32Loop;
    
    //
    // Enable Clock to Port A
    //
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    
    //
    // Wait for Some time
    //
    SysCtlDelay(10);
    
    //
    // PA2: Power Control
    // PA3: Reset Control (Open Drain)
    // PA4: TCK
    // PA5: TMS
    //
    GPIOPinTypeGPIOOutput(GPIO_PORTA_AHB_BASE,GPIO_PIN_2);
    GPIOPinTypeGPIOOutputOD(GPIO_PORTA_AHB_BASE,GPIO_PIN_3);
    GPIOPinTypeGPIOOutput(GPIO_PORTA_AHB_BASE,GPIO_PIN_4);
    GPIOPinTypeGPIOOutput(GPIO_PORTA_AHB_BASE,GPIO_PIN_5);
    
    //
    // Power Down The On Board LDO and wait for some time
    // so that VDDS and VDDA are down to 0V
    //
    GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_2,0x0);
    SysCtlDelay(10000);
    
    //
    // Make TCK Low and TMS High
    //
    GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
    GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
    
    //
    // Assert Reset and then Power Up and wait for some time
    // so that VDDS and VDDA are 3.3V
    //
    GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_3,0x0);
    GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_2,GPIO_PIN_2);
    SysCtlDelay(1000000);
    
    //
    // Run the Unlock Sequence
    //
    for(ui32Loop=0;ui32Loop<5;ui32Loop++)
    {
      PulseClock(64,1);
      JTAG2SWD();
      PulseClock(64,1);
      SWD2JTAG();
    }
    //
    // One More Pulse Train
    //
    PulseClock(64,1);
    
    //
    // Release Reset and wait for 400 ms
    //
    GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_3,GPIO_PIN_3);
    SysCtlDelay(2133333);
    
    
    //
    // Convert All Pins as Input so that external debugger
    // and LDO Control can work
    //
    GPIOPinTypeGPIOInput(GPIO_PORTA_AHB_BASE,GPIO_PIN_2);
    GPIOPinTypeGPIOInput(GPIO_PORTA_AHB_BASE,GPIO_PIN_3);
    GPIOPinTypeGPIOInput(GPIO_PORTA_AHB_BASE,GPIO_PIN_4);
    GPIOPinTypeGPIOInput(GPIO_PORTA_AHB_BASE,GPIO_PIN_5);
    
    void PulseClock(uint32_t ui32ClockPulse, uint32_t ui32TMSValue)
    {
      uint32_t ui32Loop;
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,(ui32TMSValue << 5));
      
      for(ui32Loop=0;ui32Loop<ui32ClockPulse;ui32Loop++)
      {
        GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
        SysCtlDelay(10);
        GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
        SysCtlDelay(10);
      }
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      SysCtlDelay(10);
    
    }
    
    void JTAG2SWD(void)
    {
      //
      // Send Sequence 0xE79E LSB First
      //
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
    }
    
    void SWD2JTAG(void)
    {
      //
      // Send Sequence 0xE73C LSB First
      //
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
    }
    

  • Amit Ashara said:

    Hello PAk

    Attached is the code sequence that I run on a TM4C129X with System Clock of 16MHz. This sequence is extracted from my main program, but I have tried to encapsulate the functions

    Regards

    Amit

    3806.uCUnlock.c
    uint32_t ui32Loop;
    
    //
    // Enable Clock to Port A
    //
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    
    //
    // Wait for Some time
    //
    SysCtlDelay(10);
    
    //
    // PA2: Power Control
    // PA3: Reset Control (Open Drain)
    // PA4: TCK
    // PA5: TMS
    //
    GPIOPinTypeGPIOOutput(GPIO_PORTA_AHB_BASE,GPIO_PIN_2);
    GPIOPinTypeGPIOOutputOD(GPIO_PORTA_AHB_BASE,GPIO_PIN_3);
    GPIOPinTypeGPIOOutput(GPIO_PORTA_AHB_BASE,GPIO_PIN_4);
    GPIOPinTypeGPIOOutput(GPIO_PORTA_AHB_BASE,GPIO_PIN_5);
    
    //
    // Power Down The On Board LDO and wait for some time
    // so that VDDS and VDDA are down to 0V
    //
    GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_2,0x0);
    SysCtlDelay(10000);
    
    //
    // Make TCK Low and TMS High
    //
    GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
    GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
    
    //
    // Assert Reset and then Power Up and wait for some time
    // so that VDDS and VDDA are 3.3V
    //
    GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_3,0x0);
    GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_2,GPIO_PIN_2);
    SysCtlDelay(1000000);
    
    //
    // Run the Unlock Sequence
    //
    for(ui32Loop=0;ui32Loop<5;ui32Loop++)
    {
      PulseClock(64,1);
      JTAG2SWD();
      PulseClock(64,1);
      SWD2JTAG();
    }
    //
    // One More Pulse Train
    //
    PulseClock(64,1);
    
    //
    // Release Reset and wait for 400 ms
    //
    GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_3,GPIO_PIN_3);
    SysCtlDelay(2133333);
    
    
    //
    // Convert All Pins as Input so that external debugger
    // and LDO Control can work
    //
    GPIOPinTypeGPIOInput(GPIO_PORTA_AHB_BASE,GPIO_PIN_2);
    GPIOPinTypeGPIOInput(GPIO_PORTA_AHB_BASE,GPIO_PIN_3);
    GPIOPinTypeGPIOInput(GPIO_PORTA_AHB_BASE,GPIO_PIN_4);
    GPIOPinTypeGPIOInput(GPIO_PORTA_AHB_BASE,GPIO_PIN_5);
    
    void PulseClock(uint32_t ui32ClockPulse, uint32_t ui32TMSValue)
    {
      uint32_t ui32Loop;
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,(ui32TMSValue << 5));
      
      for(ui32Loop=0;ui32Loop<ui32ClockPulse;ui32Loop++)
      {
        GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
        SysCtlDelay(10);
        GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
        SysCtlDelay(10);
      }
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      SysCtlDelay(10);
    
    }
    
    void JTAG2SWD(void)
    {
      //
      // Send Sequence 0xE79E LSB First
      //
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
    }
    
    void SWD2JTAG(void)
    {
      //
      // Send Sequence 0xE73C LSB First
      //
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,0x0);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,0x0);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
      
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_4,GPIO_PIN_4);
      GPIOPinWrite(GPIO_PORTA_AHB_BASE,GPIO_PIN_5,GPIO_PIN_5);
      SysCtlDelay(10);
    
    }
    

    Thank you Amit, will try to prepare a board and test it.

  • Amit Ashara said:

    Hello PAk,

    They are evaluating if the XDS100 gives the capability to run bare JTAG Sequences as TIVA uses JTAG-TO-SWD and SWD-TO-JTAG switching sequences which XDS100 does not supprt.

    I don't expect an answer soon either as they have multiple products to support and they indicated that it is the feature of LMFlashProgrammer that has been imported as is into UNIFLASH

    Regards

    Amit

    Hello Amit.

    Have the guys from Uniflash told you if XDS100v2 will be able to unlock Tiva devices? And any other Jtag device?

    Thank you and regards.

  • Hello PAk,

    They will try the same for UNIFLASH v3.3 as the next release (v3.2) is already ongoing and intercepting it would not be possible without delays.

    JTAG devices: you mean an emulator? If yes, then right now Stellaris ICDI is the only one. If you can get a LM3S ICDI board then it would work on that as well.

    Regards

    Amit

  • Hi again Amit.

    Do you have any new feedback from the Uniflash guys about XDS100v2 and unlocking Tiva devices?

     

    Regards

  • Hello PAk

    They have it scheduled but no release date so far from them.

    Regards

    Amit

  • Hello Amit,
    is there any news about unlocking TivaC devices?
    I unintentionally lock it, I have tried at first LM Flash Programmer as it is recommended in mcu datasheet, but there is not XDS100v2 interface :-( then I tried UniFlash (3.1.0.00026), but without success. Interesting is, that UniFlash sends only positive messages:

    [21:11:58] CORTEX_M4_0: Starting Debug Port Unlock operation...
    [21:11:58] CORTEX_M4_0: Initial Unlock completed, please release reset button and press the "Finish Unlock" button in the Flash options to complete the operation...
    [21:12:02] CORTEX_M4_0: Power cycle the board to complete the unlock procedure.

    I have this problem on one prototype, but I would not throw it away.
    Thanks.
    Jan
  • Hello Jan,

    There has been no update to UNIFLASH v3.2 for using XDS100v2 for Unlock. You may need to (if you have a Launchpad for TM4C123 or TM4C129) re-wire a Launchpad to unlock it using LMFlashProgrammer

    Regards
    Amit
  • Hello Amit,

    good advice, thanks.

    But interesting is, that I  did not use commit registers GPIOLOCK and GPIOCR (I learned about commit control registers today). How is it possible that JTAG is disabled???

    This is the code I used, nothing else regarding GPIO:

     

    // Clock Gating Control
    SYSCTL_RCGCGPIO_R = SYSCTL_PPGPIO_R; // Enable clock to peripheral present ports = all present ports
    SYSCTL_GPIOHBCTL_R = SYSCTL_PPGPIO_R;

    ...

        // PORT C
        // 7: BUTTON4
        // 6: BUTTON3
        // 5: DMX_TXD
        // 4: DMX_RXD
        // 3: JTAG_TDO
        // 2: JTAG_TDI
        // 1: JTAG_TMS
        // 0: JTAG_TCK
        GPIO_PORTC_AHB_DIR_R = 0x00; // Set the GPIO direction as input
        GPIO_PORTC_AHB_DEN_R = 0xF0; // Enable the GPIO pin for digital function.
        GPIO_PORTC_AHB_PUR_R = 0xF0; // Pull-up resistors enable
        GPIO_PORTC_AHB_AFSEL_R = 0x30; // Alternate Function UART
        GPIO_PORTC_AHB_PCTL_R = GPIO_PCTL_PC4_U4RX + GPIO_PCTL_PC5_U4TX;
        

    Jan

  • Hello Jan,

    My suspicion is the PCTL that has got changed to 0x0 is causing the JTAG Lockout.

    Regards
    Amit
  • Hello Amit, as it is not proffessional to throw a launchpad to our customers with our custom boards to unlock them, we are still waiting for a solution.

    Would it be possible to generate the unlocking sequence with a ftdi FT2232H device, since it can support JTAG protocols.
    www.ftdichip.com/.../FT2232H.htm

    In that case, have you done this already (I understand that in the first stellaris devices, some og them integrated a FTDI chip to do this task)? Do you have some instructions?

    Regards.

    PS: 

    We have seen something similar was possible to the old Luminary micro devices:
    Is it available with the new Tiva devices?
  • Hello PAk,

    Yes it should be possible. I know that the unlock sequence does work with FT2232H. The key would be to get it correctly programmed. Alternatively the LM3S ICDI can be reused.

    Regards
    Amit
  • Thank you
    Could you provide any assistance/guide on this. This issue could get solved easily and would help a lot of people/companies willing to sell your chips.

    We have never programmed that FT2232 before and probably you already have it done from the old Stellaris age.

    Thank you
  • Hello PAk,

    Following post would be a good start point.

    e2e.ti.com/.../1458104

    Regards
    Amit
  • Thank you Amit, that is a great help.

    However it is still not clear for us how to program the FTDI2232 chip to unlock Tiva devices.

    Regards

  • Hello PAk

    FTDI comes with an application called FTProg that can be used to configure the FTDI chip. The details for the settings are there in the post as well.

    Regards
    Amit
  • Hello Amit.
    I know that application, I have used it many times to change the timing settings of a FTDI chip.

    However, how can I set the unlocking sequence with it?
  • Hello PAk,

    The drivers for FTDI on the www.ti.com need to be installed when the FTDI device is plugged in.

    Regards
    Amit
  • Thank you Amit. But this is not my question.
    Once the drivers are installed, will LMflashprogrammer and Uniflash be able to generate the sequence? In that case, which is the configuration?
  • Hello PAk,

    LMFlashProgrammer will. The drivers are compatible, so it would not be an issue.

    Regards
    Amit
  • And which is the configuration for LMFlashProgrammer? ICDI?

    On the other hand, xds100v2 has a FTDI2232 device, hence why the unlocking sequence cannot be achieved with it?
  • Hello PAk,

    Yes, it would be ICDI. XDS100v2 does not expose the SWD mode of operation in the API.

    Regards
    Amit
  • Amit Ashara said:
    Hello PAk,

    Yes, it would be ICDI.

    Thank you Amit. 

    We have tried with a C232HM-DDHSL-0 cable and (a reprogrammed C232HD-DDHSP-0) with no luck to unlcok the device.

    It seems that  LMFLASHPROGRAMMER is not finding the FTDI device and is not able to unlock.

    Could you provide any help? A rough guide would be great for the community!!

    Regards.

  • Hello PAk,

    I have not used this cable so far. But can you check Device Manager is able to interpret it as a Stellaris ICDI. If not then remove the drivers and instead try to point it to the Stellaris ICDI drivers

    Regards
    Amit
  • If I might be so bold PAk, get a different JTAG adapter, you've spent enough in gold and effort on this one to justify having replaced it already.

    Robert
  • If we admit "bold" here Robert - might you be speaking toward the, "Choice & use" of a "proper tool" as opposed to a, "Bent, teased, twisted" one - tormented (almost) into normal/customary signal compliance.    (in such boldness - sometimes is found greatness!)

    If an improper ICDI - remains in the path of even a "proper JTAG/SWD" probe - ALL still may be LOST!   (i.e. one must "directly connect" the proper probe to the target MCU!)

  • Also the propriety of proprietary packaged processes.

    Robert
  • Robert Adsett said:
    Also the propriety of proprietary packaged processes.

    May we note that when we attach our (multiple) J-Links to (at least 4 different vendor's ARM MCUs) - always via SWD - each/every one responds as expected.

    As we "direct connect" to the MCU's 2 SWD pins - how/where/when may these "proprietary packaged processes" rise to torment?   (we've escaped that fate - thus far...)