SSI0 DMA Questions

I also attach my data file.

Hello Dennis,

1. No, the transfer size can be set for any value from 1-1024. The data sheets states binary steps and hence every value in this range is possible

2. A Basic Mode would be OK for such data rates.

3. I will go through the code and see if I can figure what is going on.

Regards

Amit

Hi Amit,

I set the packet length to 34 bytes and I got DMA bus error. I changed to 32 bytes the DMA bus error went away. I am not sure what could be the problem.

When I switched to basic mode, the SSI0 ISR is constantly interrupted with garbage data. In ping-pong mode, at least the data packets came in at the exact interval.

In the mean time, I will turn my ADC ISR off to see if my SPI data getting any better,

Thanks for your quick response to look at this.

Dennis

Hello Dennis

The error configuration which causes The DMA Bus Error is already a part of the zip code you have sent?

Regards

Amit

Yes. Thanks,

Dennis

Hi Amit,

I found the issue with DMA bus error. I think my ADC ISR took too long that causes SPI & DMA issues. By turning off ADC data processing I am no longer getting DMA bus error. Please consider item 1 is answered.

Please advice on item 2-4.

Thanks,

Dennis

Hi,

I actually found the DMA bus error is due my testing when I disable ADC initiailization but the TMR0 still active. I am trying to figure out item 3 and 4 and I found the behavior. I am using SSI2 master to communicate to a third micro-controller. This is a SSI blocking interface which write and read from SPI data registers. If I disable all write/read to SSI2, SSI0 Rx DMA is clean with the data rate of 250ms interval.

When I crank up the SSI0 data to 200ms interval or faster, SSI0 Rx DMA buffer seems shifted after a while.

Thanks for your inputs,

Dennis Nguyen 

Hi,

An alternate approach is for me to lower the SSI0 Interrupt than my ADC. Do you have any information to change the peripheral priority.

Thanks,

Dennis Nguyen

Hello Dennis,

You can use IntPrioritySet to lower the priority but this will have affect only when the two interrupts come at the same time. If the CPU is processing a lower priority interrupt when a higher priority interrupt comes, then it will not drop the lower priority interrupt,

Regards

Amit

Thanks, Amit. I agree and I don't think lowering the priority will help me in this scenario. I am continuing to investigate the issue of SSI0 Rx DMA data buffer intefered by SSI2. I dumped the g_uDMAControlTable[1024]. All bytes are zeros except these offset: [180]-0x8,[181]-0x80,[182]-0,[183]-0x40,[184]-0xE5,[185]-0x43,[186]-0,[187]-0x20,[188]-0,[189]-0x80,[190]-0,[191]-0xC. Regradless, SSI2 traffic is on or not the content of g_uDMAControlTable is the same.

My assumption was at the first step I am only interest for the SSI0 Rx packet. SSI0 Tx will be what ever in the Tx FIFO. With the issues existed I enable Tx uDMAChannelTransferSet in the ISR. My thought was missing Tx DMA might cause side effects. Just like my original provided code, I enable the following:

    if( !uDMAChannelIsEnabled( UDMA_CH11_SSI0TX ) )
    {
        //
        // Start another DMA transfer to TX.
        //
        uDMAChannelTransferSet( UDMA_CH11_SSI0TX | UDMA_PRI_SELECT,
                                    UDMA_MODE_BASIC, g_TxBuf,
                                    (void *)(SAF_SPI_BASE + SSI_O_DR),
                                    sizeof(g_TxBuf));

        //
        // The uDMA TX channel must be re-enabled.
        //
        uDMAChannelEnable( UDMA_CH11_SSI0TX );
    }

With this Tx code enable, I got DMA error with g_uDMAControlTable all bytes are zeros except these offset: [180]-0x8,[181]-0x80,[182]-0,[183]-0x40,[184]-0xE5,[185]-0x43,[186]-0,[187]-0x20,[188]-13,[189]-0x82,[190]-0,[191]-0xC. Off set 188 and 189 are different. Please let me know the description of these 2 bytes.

Thanks,

Dennis