ADC Digital Comparator working in Rising Edge mode but not Falling edge mode

I'm using Seq 0 for sampling data on both ADC's AIN2 on ADC0 and AIN3 on ADC1

Seq 1 is configured for generating Interrupt using Digital Comparator 0, Although both ADC are initialized only one ADC Seq 1 is enabled for interrupt generation when required

When I configure the DC for CIC = HIGH and CIM HONCE the interrupt generation happens properly at rising edge.

But when I configure DC for CIC = LOW and CIM = HONCE the interrupt is generated the moment I enable the Seq1. Is there anything wrong in the sequence of configuring/enabling various blocks

As Errata ADC#3 does not apply to TRIGGER_ALWAYS a single step has been configured.; works fine for rising edge.

****** extract from my program code

****** initialization

// Use ADC0 & ADC1 SEQ0 for Analog Channel Sampling
ROM_ADCSequenceConfigure(ADC0_BASE, 0, ADC_TRIGGER_TIMER, 0); // seq:0, priority:0
ROM_ADCSequenceConfigure(ADC1_BASE, 0, ADC_TRIGGER_TIMER, 0); // seq:0, priority:0

// Use ADC0 & ADC1 SEQ1 for Digital Comparator TRIGGER
ROM_ADCSequenceConfigure(ADC0_BASE, 1, ADC_TRIGGER_ALWAYS, 1); // seq:1, priority:1
ROM_ADCSequenceConfigure(ADC1_BASE, 1, ADC_TRIGGER_ALWAYS, 1); // seq:1, priority:1

ROM_ADCSequenceStepConfigure(ADC0_BASE,0,0,ADC_CTL_CH2|ADC_CTL_IE|ADC_CTL_END); // 
ROM_ADCSequenceStepConfigure(ADC1_BASE,0,0,ADC_CTL_CH3|ADC_CTL_IE|ADC_CTL_END);

ROM_ADCSequenceStepConfigure(ADC0_BASE,1,0,ADC_CTL_CH2|ADC_CTL_CMP0|ADC_CTL_END);
ROM_ADCSequenceStepConfigure(ADC1_BASE,1,0,ADC_CTL_CH3|ADC_CTL_CMP0|ADC_CTL_END);

********** run time config steps

ROM_ADCComparatorRegionSet(myTrigSrc, 0, myLevel, myLevel+0x80);

ROM_TimerLoadSet(WTIMER5_BASE,TIMER_A, (SYS_CLK_FREQ/myFreq) - 1);
ROM_TimerControlTrigger(WTIMER5_BASE,TIMER_A, true);

ROM_ADCSequenceEnable(ADC0_BASE, 0); // for sampling
ROM_ADCSequenceEnable(ADC1_BASE, 0);
ROM_ADCIntClear(ADC0_BASE, 0);
ROM_ADCIntEnable(ADC0_BASE, 0); // seq 0 uDMA intr enable
ROM_ADCIntClear(ADC1_BASE, 0);
ROM_ADCIntEnable(ADC1_BASE, 0);
// delay comparator
ROM_TimerEnable(WTIMER5_BASE,TIMER_A); // Sample Rate Timer Starts

******** some delay to fill sampled data before enabling Comparator (myTrigSrc is ADCx_BASE)********

if (AnalogTrigConfig & ALOG_TrigEdge) {
if (AnalogTrigConfig & ALOG_TrigLevel) { // Edge Mode
myTrig = ADC_COMP_INT_HIGH_HONCE;
} else {
myTrig = ADC_COMP_INT_LOW_HONCE;
}
} else {
if (AnalogTrigConfig & ALOG_TrigLevel) { // Level Mode
myTrig = ADC_COMP_INT_HIGH_ALWAYS;
} else {
myTrig = ADC_COMP_INT_LOW_ALWAYS;
}
}

ROM_ADCComparatorRegionSet(myTrigSrc, 0, myLevel, myLevel+0x80);
ROM_ADCComparatorConfigure(myTrigSrc, 0, myTrig );

ROM_ADCComparatorReset(myTrigSrc, 0, true, true);
ROM_ADCComparatorIntClear(myTrigSrc, ROM_ADCComparatorIntStatus(myTrigSrc));
ROM_ADCIntClear(myTrigSrc, 1);
ROM_ADCComparatorIntEnable(myTrigSrc, 1);
ROM_ADCIntEnable(myTrigSrc, 1);
ROM_ADCSequenceEnable(myTrigSrc, 1);