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Reading 32bit frame on a SSI Line with uDMA

PAk
Mastermind 6995 points
Other Parts Discussed in Thread: TM4C129ENCPDT

Reading 32bit frame on a SSI Line with uDMA

 

Hello.

We are communicating with a remote SPI ADC device from a Tiva TM4c129X chip. We have configured the Tiva board to read one 16bit frame continuosly (at the sampling frequency  rate) in 512 samples blocks via uDMA, with a pingpong buffer without effort.

Our objective is to be able to read two adcs channels to get stereo processing, to do that we need to read a frame with this format:

 

 

However, SSI on Tiva only accepts 16-bit frames, so it we cannot read the frames the same way we are doing it now.

We know we could set a GPIO as CS line, and control it manually, but then we would lose the implementation with the dma, so we would have an interrupt for every sample we get, having a large overhead of processor time, which we cannot “afford”.

 

Is there any register+udma setting that could allow us to do this?

Also, could the frame be “cut” in the middle, receive it via dma and arrange it later into two samples?

Thank you.

  • 0
    TI__Guru**** 244380 points

    Hello PAk

    SSI does not support more than 16-bits. So as you mentioned it is required to have the CS being controlled by a GPIO. There is no register+udma setting to do that.

    You can use the SSI word size as 16-bit with Increment set to half-word for the uDMA to pack the byte.

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Mastermind 6995 points

    Amit Ashara said:

    Hello PAk

    SSI does not support more than 16-bits. So as you mentioned it is required to have the CS being controlled by a GPIO. There is no register+udma setting to do that.

    You can use the SSI word size as 16-bit with Increment set to half-word for the uDMA to pack the byte.

    Regards

    Amit

    Thank you Amit.

    Another way using this ADC could be reading each channel on a different line (using two 16-bit line).

    Is it possible to configure just one SSI, receiving via 2 Rx pins of data?

    I mean, for example, using SSI0 and using the pins:

    SSI0CLK

    SSI0FSS

    SSI0TX

    SSI0RX1

    SSI0RX2

    Regards

  • 0 in reply to PAk
    TI__Guru**** 244380 points

    Hello PAk

    No it is not possible for the SSI core to do so.

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Mastermind 6995 points

    Amit Ashara said:

    Hello PAk

    No it is not possible for the SSI core to do so.

    Regards

    Amit

    Thank you Amit.

    It seems that enabling 2 SSI ports (one as clk master and one as slave) is the way to go for us, right?

    Could you provide an example of a QSSI application? Perhaps a diagram?

    Regards.

  • 0 in reply to PAk
    TI__Guru**** 244380 points

    Hello PAk

    Are you using aTM4C129 or a TM4C123 device? QSSI is valid for TM4C129 devices only.

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Mastermind 6995 points

    Amit Ashara said:
    Are you using aTM4C129 or a TM4C123 device? QSSI is valid for TM4C129 devices only.

    A TM4C129ENCPDT

  • 0 in reply to PAk
    TI__Guru**** 244380 points

    Hello PAk,

    Is there a requirement to Transmit to the ADC? I am asking this since we can optimize the QSSI for Rx only operations if Tx is not required?

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Mastermind 6995 points

    Amit Ashara said:

    Hello PAk,

    Is there a requirement to Transmit to the ADC? I am asking this since we can optimize the QSSI for Rx only operations if Tx is not required?

    Regards

    Amit

    Hello Amit.

    NO tx at all, we just want to receive two 16 bit lines. However, we have to be the master of the ski bus (providing clk and fss)

    Thank you.ñ

  • 0 in reply to PAk
    TI__Guru**** 244380 points

    Hello PAk,

    You can use the Single Master as Bi Mode RX only and connect RX0 to one ADC and RX1 to another ADC. The bits shifted in would be alternating between the two ADC for every byte.

    Byte-0:ADC1,ADC0,ADC1,ADC0,ADC1,ADC0,ADC1,ADC0

    Byte-1:ADC1,ADC0,ADC1,ADC0,ADC1,ADC0,ADC1,ADC0

    ...

    Byte-7:ADC1,ADC0,ADC1,ADC0,ADC1,ADC0,ADC1,ADC0

    The software then has to mask and shift the bits. Other than this you would need to use SPI Masters

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Mastermind 6995 points

    Ok. That would work.

    Could you provide a snippet of code about how to setup adc and udma?

    Thank you.

  • 0 in reply to PAk
    TI__Guru**** 244380 points

    Hello PAk,

    This is a code snippet. You may have to tweak it :-)

    uint32_t ui32DummyData, ui32ReadData[8];

    ui32DummyData = 0;

    SSIAdvFrameHoldEnable(SSI0_BASE);

    SSIAdvModeSet(SSI0_BASE,SSI_ADV_MODE_BI_READ);

    for(ui32Count=0;ui32Count<7;ui32Count++)

    {

      SSIDataPut(SSI0_BASE,&ui32DummyData);

      SSIDataGet(SSI0_BASE,&ui32ReadData[ui32Count]);

    }

    SSIAdvDataPutFrameEnd(SSI0_BASE,&ui32DummyData);

    SSIDataGet(SSI0_BASE,&ui32ReadData[7]);

    for(ui32Loop=0;ui32Loop<8;ui32Loop++)

    {

      for(ui32Count=0;ui32Count<8;ui32Count++)

      {

        if(ui32Count%2 == 0)

        {

         ui32Temp = (ui32ReadData[ui32Loop] >> ui32Count) & 0x1;

         ui32ADC0Data |= ui32Temp << ((ui32Count/2)+4*ui32Loop);

      }

      else

      {

         ui32Temp = (ui32ReadData[ui32Loop] >> ui32Count) & 0x1;

         ui32ADC1Data |= ui32Temp << ((ui32Count/2)+4*ui32Loop);

      }

    }

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Mastermind 6995 points

    But can we read 16 bits messages this way or just 8?

    Which are the parameters for the udma to get continuously reading? I mean arb size,etc...

  • 0 in reply to PAk
    TI__Guru**** 244380 points

    Hello PAk

    We can read only 8 bit messages and that to in FRF0 format.

    For using the UDMA you can use ARB Size of 4 with transfer size of 4 for both TX and RX. For TX you can use constant addressing to write 0x00 so that the SSI can be throttled to push in the data

    Regards

    Amit