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Tiva GPIO Equivalent Circuit, Tri-State and Resistance/Capacitance Characteristics

Other Parts Discussed in Thread: TM4C123GH6PM, EK-TM4C123GXL

Hi.

Using Tiva TM4C123GH6PM part on Tiva Launchpad Evaluation Kit EK-TM4C123GXL

1) Although there are volumes of documentation on the Tiva series parts, I have been unable to discover how I might, with certainty, tri-state a GPIO when set as output.

Would using the DEN register achieve this?

2) Is there any documentation that gives an indication of the nature of the gpio pin's electronic circuitry?

2a) In particular, is the output normally configured as a totem pole unless the open drain is enabled? Or something else?

2b) What are the equivalent series resistances to Vdd and Gnd when the output pin is HIGH and LOW respectively (and not configured as open drain)? Testing indicates that the equivalent resistance to ground might be in the region of 29 Ohms when low and around 33 Ohms to Vdd when high. Would these values be correct? Is there much variance from port to port (pin to pin) and across parts?

2c) What might be the effective capacitance on the pin when configured as an input? Likewise with the variance question of 2b.

I hope I have not missed details of all these matters somewhere in the documentation.

Thank you for considering these questions.

Take care.

Mike

  • Always there's danger when poster seeks reponse deemed useful or, "with certainty."  (a la - this poster)

    Thus - with as much certainty as vendor's manual (and my experience) may provide - I present:

    Mid item - above chart - shows required Register settings.  (your DEN Register appears non-major factor - in this case)  Far more crucial is ODR Register - which switches the output circuitry to, "Open Drain."

    Vendor's well established library code automates (via encapsulation) this setting - insures all key registers are properly configured - vastly superior to your "direct register" usage.  (no offense - simple "strength in numbers" of long test/verified encoding - individual user efforts - not so much!)

    I made the effort to quickly review vendor's tech detail (cheap seats - far down MCU manual) seeking further answers - no such relevant detail (as you reported) provided.

    Our firm has (or has access to) fairly advanced equipment - suspect able to make such measurements.  Might you describe your need?   If beneficial to enough users here - we may test & report as time/work-load allows...

  • Thank you very much for the above information.

    I don't believe the ODR register would satisfy the requirement for a Tri-state output.  I believe the ODR register would merely swap between an open-drain output configuration and 'something else' which is not defined or explained anywhere else as far as I could find but which may be a totem-pole configuration.

    If this is a totem-pole configuration and the pin is configured for output then whatever the data register contains will drive the output either low or high. 

    Not tri-state the output.

    So...

    ...how do I tri-state the output?

    Thank you again for your response.

    Take care.

    Mike

  • Hi,

    from my knowledge of MCU's their input part of the pad is always active. The output part (totem pole) can be disabled (tri-stated) by selecting input direction in GPIODIR. 

    A GPIO pin is always in input or output state where the output state can have different options like open drain, drive strength etc.

    /Michael

  • Hello Michael

    The TM4C GPIO's work as output when GPIODIR bit is set (all poster's have identified this) and do not have tri state control in GPIO Mode

    2a. and 2b There is no such diagram or data

    2c. The Electrical Characteristics -> Input/Output Pin Characteristics -> Table GPIO Module Characteristices -> Parameter CGPIO

    However to achieve tristate control you would need to use the GPIODIR and GPIODATA (when driving) registers together (as all mentioned) or use the GPIOODR register open-drain function (as mentioned by cb1)

    Regards

    Amit

  • Thank you Amit.

    2a/2b - Shouldn't there be such a diagram?

    2c. - Thank you. Somehow I missed that.

    I do not understand how GPIODIR and GPIODATA could be used to create a tri-state output.

    If GPIODIR is set to output (as required) then when GPIODATA is high, output is high and when low output is low, neither of which is tri-state.

    If using GPIOODR then the output is open drain when set or 'normal' (whatever that is) when not. So if my output is low and I need to tristate the output then switching to open drain would just keep the output low.

    What is the purpose of the DEN register?

    Would this tri-state the output, assuming analogue and alternate functions are not enabled?

    Having an equivalent circuit of the pin circuitry would be really helpful

    Thanks again.

    Take care.

    Mike

  • Michael Malone1 said:
    if output is low and need to tristate - the output then switching to open drain would just keep the output low.

    This may be a good illustration of, "reductio ad absurdum."

    And - by that logic - pedestrian crossing against traffic (w/out looking) in NYC's rush hour - would be unlikely to arrive safely!  

    Of course - to properly order that gpio into tri-state - you'd drive the logic level to the appropriate level "prior" to asserting, "open drain!"

    In the spirit of assisting you to, "best/brightest" solution - might I suggest that (most any) MCU provides (as the name well implies) "General Purpose Inputs/Outputs."  There exist buffer ICs - which are more likely to provide the very specialized output characteristics - you appear to seek.  (and these may buffer an entire, 8 bit port...)

  • So are you saying the the official method to tristate a gpio in a tiva series part is to first drive the pin high and then to make it open drain?

    What if the first action - driving the pin high - would cause problems with the logic in the external circuitry at that time?

    Surely there must be a better way?

    It is not uncommon to have a need to tristate an output. In my experience it is very common.

    Even basic mcus provide that capability via their gpios without requiring specialised ics with their associated part and board costs.

    Or are you saying that the more 'advanced' ARM Tiva parts cannot achieve this basic need?

    Thank you for your reply.

    Take care.

    Mike

  • My friend - I'm simple "user/specifier" much like you.  I never intend to speak for the vendor - I was careful to note such in my opening response.

    Forcing the gpio into its, "normal/customary" input state does insure a "reasonable" high impedance.  From that input state - as/if/when required - that gpio may be configured as "open drain output." 

    Should state that our small tech group works w/many ARM MCUs - many vendors - we've not noted any major limitations with this vendor's devices (in your specific I/O regard). 

    I'm very much against, "MCU as kitchen sink" - 8 bit buffers are inexpensive - should satisfy even the most exacting, "tri-state needs/desires."  Cost/size "penalty" imposed easily meets my group's, "Risk-Reward" matrix.  That's my recommendation - wish you well...

  • Thank you again for your response.

    But can someone from ti perhaps answer some simple questions, please?

    What is the equivalent circuit of the pin when not in open drain mode? Is it a totem pole? If so, is there a disable/enable of the two driving transistors in this circuit? Does the DEN register achieve this? Or some other register? Or is this not possible?

    Cents add up. Adding parts that cost more than the ARM Tiva cpu is not always an option (materials management, part cost, production costs, board costs, larger enclosure, etc all add up).

    If an 8-bitter like an ATmega can tristate its gpios - thus helping make them gpios - surely an ARM Tiva can?

    Does anyone know the equivalent pin circuitry in the Tiva? Or is it a secret?

    Thanks again for all the replies. 

    Take care.

    Mike

  • Hello Mike,

    The GPIODEN register is the master control for the Digital path. So if the GPIODEN is cleared then GPIODATA cannot be used in read/write mode. If the GPIODEN is set then with GPIODIR=0 the IO remains in tristate mode and output path disabled. If the GPIODEN is set with the GPIODIR=1 then IO is in output mode with the pad value now reflecting on the input path.

    Regards

    Amit

  • Thank you Amit.

    I also came across this 

    http://e2e.ti.com/support/microcontrollers/stellaris_arm/f/471/t/89953.aspx

    It seems odd that TI did not include a means to specifically tri-state a pin. It is a common requirement, after all. And it is not as if there has been any reluctance to include registers in the Tiva series - there are 36 registers for each port as it is.

    However, in the interim one of our guys has found an alternate series of ARM parts that provide a better match of peripherals for what we need to do allowing us to create a wider range of products than we could have hoped (and specifically tri-state outputs too).

    So it looks like the gods were looking after us on this one :)

    Many thanks for your help.

    Take care.

    Mike 

  • Michael Malone1 said:
    Cents add up. Adding parts that cost more than the ARM Tiva cpu is not always an option

    Glad that - with your new "find" - you're (now) content.  Realize that you've never provided the ancillary detail (requested) justifying, "why you believe" such full/total tri-state control is so vital. 

    I'd strongly dispute your statement (quoted above) for many/most (likely all) here.  Should the cost/size "penalty" imposed by an 8 bit buffer IC erode your product's profitability - your effort is very likely miscast.  (I state this having past founded several tech firms - most continuing today - and having taken one, "public!")   Perhaps you (can) find an 8 bit buffer (24K gold-plated) which exceeds MCU's cost - (that appears your argument) - which no VC would buy!

    Yes it's important to "sweat the details" - but over-emphasis on "minority" issues too often delays products' design/release - missing the all important, "sweet-spot" of early/advantaged (thus highest profit) product launch! 

    At any rate - group here has well responded - wish you well...

  • Michael Malone1 said:
    It seems odd that TI did not include a means to specifically tri-state a pin.

    On all the micros that I have worked with tri-state output was synonomous with setting the pin to input (with any pull-ups disabled if applicable) and in fact it is the state almost all I/O pins on a micro normal start in on power-on and reset.

    The only significant difference I am aware of between a tri-state input and a tri-state output is the presence of an input buffer and I can't see whay that would be an issue. Is there some other difference you are thinking of? I suppose it might add some capacitance but that difference might be swamped by variation between product lines and would have to be checked in any case if it was important.

     

    Robert