CCS6 Debug problem

Has that, "other/target" board proper, external JTAG pull-up Rs?  (i.e. 2K7-10K)

While claim is made that MCU's "weak, internal pull-ups "work"" - that proves not always the case.  (they're much higher in resistance - thus clock/data edges are rounded & noise susceptibility increases.)

Unstated is how "loaded" your power supply is.  Might the two boards be powered from one source - and one or both of the 3V3 MCU regulators are, "dropping out" during "step by step?"  (We've seen both cases (above many, many times and this "drop out" less often - yet remains "in play.")

No pull-up on TCK and TMS lines... :(

On Monday I will try putting them and I will tell you if it works.

Regarding power supply, the target board has is own 3V3.

Thank you for your support!

Hi Amit, now without optimization it seems to work fine. So what do you suggest? Disabling optimization for debugging and enabling it for release? Or keep it off all the time? Or do you know how to fix this problem?

Thank you.

Hello Davide

As I understood the issue, it was in debugging mode the CCS did not step correctly. In the release build you can switch on the optimization and run it as is

Regards

Amit

Hi Amit, you understood right. The problem is solved. Thank you very much.

But this is a bug, isn't it? If optimization does not allow correct debug, there should be a warning, at least.

Hello Davide,

I would suggest filing the same in CCS Forum. They would be able to provide a resolution from the tool side.

Regards

Amit