Tiva 129 concurrent I&Q sampling

Not sure if this is welcome here, but ST's F3 and F4 devices have modes to synchronize 2 or 3 ADCs (each ADC with theoretically 13 .. 24 channels). Search for "interleaved mode".

Hello Tim,

To synchronize channel sampling between the sequencers, the correct method would be to use processor triggering. The bandwidth will be less than 1MSPS but it would be synchronized. You can synchronize two channels with both the ADC's combined.

Regards

Amit

Thanks Amit.  If I understand what you are suggesting then this will not work for us.

We require 1 megasample per second, continuous sampling, with minimal jitter.  And, while performing the sampling, we must have the processor engaged in the signal processing demodulation.

Do we have any other options?

Hello Tim,

If a maximal delay of 1 clock cycle is acceptable then you can use timer triggered sampling for both the ADC's. This way the CPU will be available for processing the data while the timer ensure a continuous conversion.

In terms of the jitter from the original post, the same would be higher in your case as you are providing an input o 100Khz. However once you determine the phase shift between the two channels, then you can use delayed sampling using ADCSPC to get the phase in much closer proximity.

Regards

Amit

Hello Amit,

We've tried two things;  both have tested well but there may be some probability that they could fail based on the underlying workings within the Tiva 129.  First, rather than calling ROM functions to enable the ADCs, we've done this more directly:

   ROM_IntMasterDisable ();
   *((volatile unsigned long *)(ADC0_BASE + ADC_O_ACTSS)) = 0x101 << 0;
   *((volatile unsigned long *)(ADC1_BASE + ADC_O_ACTSS)) = 0x101 << 0;
   ROM_IntMasterEnable();

We use only sequencer 0, and with modest optimzation under GCC this results in two consecutive stores to the control registers.  This eliminates the function call and return overhead, as well as reading the old ACTSS register and or'ing in the new value. Here we are enabling both the dma and sequencer for sequencer 0 with a single store for each DMA channel. Testing shows that this has eliminated the phase delay.

Alternately, we've also experimented with timer triggering, enabling the timer as the last step, and using a sample rate of 1 megasample per second. We've not observed any unusual jitter or skew between ADCs with this configuration.  The timer is driven from the 480 MHz divided down.

Should we be cautious with either of these two approaches?

Regards,

Tim

Hello Tim,

In the procedure 1, the delay in sampling will be the write to the two control registers. This would be the minimum which can be offset as I mentioned earlier by using Phase Shift. The timer method will have the same affect,

However while on one device it may work well, the other device when going for mass-production may exhibit 1=few clock cycle additional delay depending on the system clock v/s clock invariance synchronizer's delay.

Regards

Amit

Thanks, Amit, for the continued interaction on this.

With method 1, we see 0 delay.  The Tiva core is at 120 MHz, the ADC is at 16 or 32.  I am curious about a note in the ADC documentation that indicates the ADCs cannot operate at different clock rates (that is, choose 16 for both, or 32 for both).  Does this coupling imply a single, underlying clock divisor for both ADC channels?

If I understand your concern, it is though this may work now, it relies on behaviour that is not necessarily guaranteed in future devices.

My understanding regarding the phase shift is that it is with reference to the trigger signal; in method 1 both channels operate in "trigger always" mode.  In mode 2 the trigger is a timer generating a trigger at 1 MHz. I've not observed any jitter in this mode; if option 1 is unwise then are there concerns with triggering the ADCs at 1 megasample per sec using a timer?

Regards,

Tim

Hello Tim,

On the TM4C129 I believe they can operate at independent clock rates as the ADCCC register is per peripheral

Regards

Amit

Hello Amit,

I would have thought so, too, except for the last sentence in 18.3.2.7 (module clocking) of the 129 manual states that the ADCs do not run at different conversion rates.

Tim

Hello Tim,

Let me check back to see if this a documentation error or the case. It could be the case when Sync bit between the ADC's need to be used, but otherwise they should be independent.

Regards

Amit