Other Parts Discussed in Thread: INA240, LM3S8971, DRV8305, INA282
Can TI please provide a better illustration of the dead band generators and delay counters structural gating and timing logic so embedded software can be made to properly control them?
Dead band generator PWMA input won't trigger on a rising edge per data sheet 23.3.5 figure 23-6 as no delay even occurs in the output of PWMENABLE bits if the PWMnDBCTRL is enabled after setting those bits high. The setup of the PMWA delay should be done when the binary code change is presented to the output pins of MCU but that is not physically possible, so the dead band cart comes before the PWM horse If you will.
Dead band delay of signal output PWM0-A actually seem to occur on the next falling edge of PWMA when specific PWMENABLE outputs are thus local synchronous updated by PWM0 generators.
More specifically if PWMnDBCTRL is used to control signal delay of PWMA in cyclic calls which enable the DBCTRL bit after the rising edge of PWMA bits are set high in PWMENABLE has no effect to delay the signal.
Only after these output bits are first switched low does PWMA signal then have a pulse width increased by the delay period set in PWMnDBRISE/FALL registers. That behavior seems to indicate the dead band delay counters only trigger when the PWMA edge changes from high to low (falling edge) and not low to high (rising edge) as stated 23.3.5. Figure 23.2 shows PWM0 generators dead band structures exist before the PWMENABLE register which connects signals to MCU pins and there is no delay counter reaction to a pin state change on the rising edge of a binary code change in PWMENABLE register to set up a delay for the falling edge event of PWMA via embedded SW.
We must insert the delay (extend the pulse width) on the high to low transition of FET gates to ensure all FET are actually off for the next turn on in order to avoid inverter shoot through of a single generator.
So it also seems the structure is of incorrect design in order to achieve better control of the output pin state delay and the embedded SW engineer is forced to control both PWMA/B delays together when they should be separate enable bits.