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TM4C1294NCPDT: Power Up Issue for TM4C1294

Part Number: TM4C1294NCPDT
Other Parts Discussed in Thread: LP5907, SN74LVC125A

Hello

We are facing a problem when power up TM4C1294, some device were not work properly.

The following errata looks like the problem we faced.

It's very difficult to reach 100us soft-start, did you have other solution? 

SYSCTL#09 Some Devices may not Start Properly During Power up

Description: In very rare cases, the internal LDOs may not start properly during power up. If the LDOs do not start properly, the device may not begin operating, and VDDC may not reach its specified levels.

Workaround(s): Power cycle the device until the device starts up correctly. This issue has not been seen on devices when the VDD rise time from 0 V to 3.0 V is less than 100 us. However, meeting this condition does not guarantee that the issue will not occur.

Thanks,

John

  • John,

    Can you post a scope capture of your power ramp up?

    If you really have that much trouble having a decent power up, then you will probably need a separate power supply, with an enable control that turns it on only after the rest of your system has adequate voltage for your MCU.

    Bruno

  • May I note that there are methods to "better achieve" your required (agreed, substantial) VDD ramp-up time. In many/most cases - the required "charging" of the power supply's Filter Caps - requires "Start-Up" current levels - (often) far in excess of their "normal" output current levels.

    Another or integrated approach sees your "power control turn-on device" applying brief yet "building" voltage pulses to these Caps - so that they assume a "pre-charge voltage level" - which then better accommodates your required, "Faster Ramp-Up of VDD."

    Your "findings" - claimed to be "very rare" - may sound against such (rare) claim - and will enforce extra time, effort, cost upon your group...
  • Hi Bruno,

    I have tried to modify schematic as your suggestion, the rising time of power up could reach up to 70us.

    Unfortunately, the problem still happened for one time within thousandth power up.

    Thanks,

    John

  • Erratum SYSCTL#09 only applies to silicon revision 1 and is very rare. We are currently shipping revision 3 silicon. Is the device you see this problem on revision 1 silicon? If not, this is something different. Can you connect with a JTAG debugger when the device has failed to startup properly?
  • John,
    From your available description, we can still only guess...
    Two thoughts here:
    - There can be something on your firmware, maybe a fault peripheral initialization that happens randomly because the crystal is not identical to the others? Debugging the faulty board might tell you that.
    - The power supply is not reaching the required value at VDDA in due time, for "1 out of 1000" of your capacitors are slightly damaged and taking too long to charge?
    Would you like to post a print of your power supply schematic so that the forum can take a look?
    Bruno
  • Would not a more "in depth" understanding be gleaned by, "Swapping the MCU from a good board with one from a failing board?" Indeed (some) effort is involved - but if the issue, "Migrates w/the MCU" - the MCU stands (very much) "Tried & Guilty!"

    Note that vendor "admits" the existence of said issue - might those "failing devices" bear the (past/failing prone) date code?      Should this prove an (other) component issue - it is expected that a "higher rate of failure" would appear & be noted - thus the MCU (alone) rises to PRIME Suspect.    (likely the sole suspect)

    All other methods prove too indirect, too slow, even wasteful!      Sometimes a "brutal approach" (as described) cuts quickly/effectively/deeply to the "Issue's heart" - thus should receive TOP consideration...

  • Hello Bob and Bruno,

    I already separated P3V3 by MOSFET, so it turns on directly once P3V3 stable and rising is very fast now.

    You can refer to the waveform that captured P3V3 and P1V2 of MCU's internal LDO in attachment.

    Sometime P1V2 power up looks not good.

    May I know is those errata for SYSCTL#09 and SYSCTL#16 been fixed in revision 3?

    Thank you,

    John

    TM4C1294 LDO Waveform.docx

  • John,
    Bob confirmed above that SYSCTL#09 has been fixed. You can also check about #16, I don't have a local copy of the document and TI's site is under maintenance at the moment.
    Do you have enough capacitors on your 1.2V LDO line? Are they placed as per recommendations? Further, are they GOOD? Slightly bridged pins on the MCU solder???
    I haven't came across this issue, nor have seen it as a popular thing in the forum, it might be related to your hardware assembly...
    Regards
    Bruno
  • Hello Bruno,

    Yes, capacitors were in the range of datasheet's recommendation. As your guessed, today I have tried removing capacitors to verify, but result is not good, the problem still happened.

    There are good parts, no any soldering issue.

    Could you please help to confirm is the #16 also been fixed in revision 3? How do you confirm the issue been fixed already? by DC ON/OFF testing? or by simulation?

    I will continue to check hardware design.

    Thanks,
    John

  • John Chen65 said:
    Could you please help to confirm is the #16 also been fixed in revision 3? How do you confirm the issue been fixed already?

    The link to the most recent errata is www.ti.com/.../spmz850g.pdf

    Just like the copy of the errata I had from 3 years ago, it indeed appears that #16 is in fact a long gone issue, not present in Rev3 silicon.

    Do you have a separate line for VDDA? Maybe if you post an image of the power section of your schematics someone will notice something wrong... The other "mysterious" possible reasons are improper handling of the device along the assembly line, moisture, and all these "much harder factors to discover by evaluating one single sample"...

    Bruno

  • Hello Bruno,

    Sure, I will provide schematic later.

    Currently, the VDDA is connected to VDD together and confirmed the rising time is about 70us without any non-monotonic.

    You can refer to the waveforms I provieded in previous replied, the VDD looks quickly and smooth ramp up.

    Just would like to know If the VDD is perfect to startup, why the VDDC startup looks not smooth?  Should it source from VDD? Which signal also will influence VDDC's startup?

    Thanks,

    John

  • Hello Bruno,

    Please refer to the power section for TM4C123 and TM4C1294 in attachment.

    We are facing this problem in TM4C1294 but didn't found in TM4C123, the errata and schematic were similar.

    Is it really fixed the errata SYSCTL#09? or only like the errata description "However, meeting this condition does not guarantee that the issue will not occur." ?

    Just would like to know it really fixed.

    Thanks,

    John

    8372.Schematic.docx

  • John,

    The schematic looks fine. Just two points on the 129:
    - #Wake: we WPU down it to GND
    - Is there a proper 4.87k RBIAS?

    The text on errata says it is fixed: the errata DOES NOT affect Rev3.

    Bruno
  • Hi

    We have a strange problem with the TM4C1294NCPDT. We are using it to communicate with digital sensors (Digital Kionix on SPI). There are situations when there is a problem with reading out the value of some of the sensors (they pass the initialization), lets say from the 20 time power up 5-6 times we can read out the value form a parts of the sensor.And this problem is happening only with 1 sensor device at one time (so the others are all good), and on some next power up, this problem happens to some other sensor.

    As the first step we look at this problem as a Firmware issue, so we fix all possible related problems as it is written down in the errata at the Appendix3. The reading out problems are decreased, but it is still happening and its about 2-3times /20 power up.

    What we discover , is that this problem is not happening when we  RESET the TIVA (Hw  reset ,with the same electronic config as in the EVM).So from 20 reset, all the time was a good communication with the sensors.

    So we begin to look for some powering issues, and found a strange situation.

    The VDDC rise time is about 10us. But the VDD rise time is more longer than you specify it in the previous chats.It is about 6ms.

    The picture from the scope(Blue-VDD, Yellow- VDDC)

    Could our problem be related to this power up situation with the TIVA? Or this value of the VDD rise time is still accepted (as in the data sheet there is no maximum value), and to look for the problem in the other parts (power supply for the sensors, etc...)

    Thanks you!

    Lou

  • It is possible with that slow rise of the 3.3V supply that the part will start operating before you get really good levels on the IO pins. Can you add an SPI CLK signal to the power-on picture above? The question is if SPI communication starts before the 3.3V supply is stable. The levels on the SPI CLK and master out signals may be marginal for your sensors if that happens.

  • Do you have an external supervisory IC? You really should.

    Robert
  • The relative "flatness" of VDD's "rise" suggests that the 3V3 Regulator may be "over-challenged." (i.e. too much current is being drawn during the "power-up" process.)

    Does this happen upon multiple boards - and from (different) builds?

    Are your sensors (all) powered from the same voltage regulator? And - if that's so - is the current demand w/in the regulator's spec?
  • Or the supply is challenged by the bulk capacitance.

    The change in slope also suggests that there is a jump in the current draw when the core powers up.

    Robert

    The slow rise might be acceptable if the micro is kept in reset until the supply is stable.
  • Hi All!

    We measure the starting of the digital communication (initialization ) -we put a LED turn ON/OFF, and measure that with scope. So we are well after that power up period, the picture is attached.

    We have separate power supply LDO (LP5907) for the TIVA, and for the digital sensors.

    We dont have any external power control circuit.

    Today we try to increase the delays between the initialization of the sensors, etc, but does not helps.

    Currently we are thinking to keep the TIVA in reset for a longer period on the start-up. Could we do this by changing the RC network element values (10k-0.1uF)on the pin70 (RST). On which voltage level on this pin is the TIVA in reset stage(i suppose the logical 0 is not only the 0V, but it in some range.. i dont found it in the data sheet)?

    Best Regards

    Lou

  • Starting from power-on, the RST pin behaves as power-on reset and the level is defined in table 27-13. However since the SPI does not start until Vdd is good, I don't think that is the problem. If the sensors are on a different power supply, is it possible that they see glitches on the SPICLK or chip select edges when the TM4C powers on that gets one of them out of sync?

  • Hi

    I modify the external reset circuit element values, winch are connected onto the RST pin on the TIVA.

    The EVM values was 1k-0.1uf, i change the 10k resistor onot 200k.

    With this we got the situation on the RST line as:

    From here as we see the TIVA should be in reset at least 10ms- the 1.98 Voltage reached on the RST line is about 10ms after its 3.3V power is stabilized.

    I found one mistake in the schematics: for the VDDC LDO capacitance we put 1uF+0.1uF+10nF, so i put 2 pcs more 1uF on it parallel, so it should be now 3uF.

    But even even with this we have the similar problems.

    The scope picture from the 3.3V power and the 1.2V VDDC is:

    For the 3.3V rising we found out that the problem source is after our DC/DC converter, the voltage reaches our LP5907 with the same rising ramp, so the output on this LP is similar to the input.

    As i say the SPI communication only starts after the power up period (i attach some picture in last post), the CS lines are all pulled UP on 3.3V on the SN74LVC125A which are located between the TIVA and the sensors. All the gates are selected with this CS, so till it is not pulled down there should be no communication on any SPI line between TIVA and the Sensors.

    Best Regards

    Lou

  • Hi all!
    After we modify the RC circuit on the RST line (put 100k with 1uF), the TIVA power ON is now a little bit delayed(we achieve the 1.9V at about 80ms). As we test with the digital sensors, we found still some problems. During the testing period we contact the digital sensor manufacturer, and its looks like the sensor itself has some bug regarding its startup... So on the end its looks like there was more problem with the sensor itself than with the TIVA start up...
    Thanks for all your comments!
    Best Regards
    Lou