TM4C1294NCPDT: construction of internal clock source

I can offer some informed speculation, but it's not much more than that.

There is explicitly a PLL for higher frequencies (I think that can be fed from the internal oscillator, but you'd have to check if you were concerned)

Crystal and MEMs are pretty much ruled out by the low accuracy of the internal clock.

That leaves an on board oscillator from embedded circuit components, these are often timed using an embedded RC. Since these are difficult to make accurately you have a reduced accuracy device compared to the mechanical MEMS and quartz crystal alternatives.

Robert

TI will hopefully chime in with something definitive. They may have insight into other potential problem areas such as case or maybe even metalization.

Hi Mat,

There are 2 built in oscillators (PIOSC , LFIOSC ) one might speculate not a crystal used on either one, rather a ceramic resonator for the 16Mhz PIOSC and LFIOSC a ceramic cap & resistor (RC) time constant. The PIOSC can drive the PLL yet the LFIOSC can not. The LFIOSC frequency is characterized as 33 kHz nominal, 10 kHz minimum and 90 kHz maximum.

Extreme atmospheric pressure as in under water or outer space in the rings surrounding Jupiter? One might think either one is a gamble with this MCU. Perhaps typical MCU use in either environment might suggest a military or even NASA certification as to such pressure being tolerated.

Very odd there were no reply to this post even after I pressed post & page updated yet your time of post was well before my post time seems very off.

Very disappointed PIOS oscillator governed by RC time constant and seems very wrong for an MCU that can top 85*c. Seemingly even an X5R ceramic cap & precision resistor would drift by several % (+/-PPS) at the higher end of MCU temperature range. Does not a ceramic resonator maintain precision over a broader temperature range than a basic OSC governed by an RC time constant? At least that was the idea behind choosing a ceramic resonator for (precision) over designs with RC time constant, was mainly to keeping the clock from drifting with temperature change. 

BP101 said:

Does not a ceramic resonator maintain precision over a broader temperature range than a basic OSC governed by an RC time constant?

Yes, but that would require a multi-part package which would add considerably to the cost.

You should have noted that the data sheet specs are not as good as you would expect from a resonator (+/- 10% over temperature).

Robert

Robert Adsett said:

Yes, but that would require a multi-part package which would add considerably to the cost.

Are you certain they can't incorporate a ceramic resonator straight into the die these days?

Had simply believed the use of word Precision describes an oscillator either governed by XTAL or Ceramic resonator at it's heart, not an RC time constant.

Even with 1% ceramic cap, how is 4.5% @16Mhz (Factory Calibration) ever maintained or even 1% via recalibration at specific temperature. Seemingly if software made constant updates to factory calibration relative to MCU temperature changes the 1% could be indefinitely maintained over the entire range.

BP101 said:

Robert Adsett

Yes, but that would require a multi-part package which would add considerably to the cost.

Are you certain they can't incorporate a ceramic resonator straight into the die these days?

Pretty certain. It would be another set of processing techniques and I think the temperatures for firing ceramics are likely incompatible with maintaining pn junctions. As well the incorporation of a resonator would come close to eliminating the need for a crystal and that would be a point to crow about. I've not seen any manufacturer mention such.

All of the precision on chip MCU oscillators I've seen have been RC based and none, despite the precision moniker, have been good enough for UART use. Although possibly good enough for LIN.

BP101 said:

Had simply believed the use of word Precision describes an oscillator either governed by XTAL or Ceramic resonator at it's heart, not an RC time constant.

Reading the data sheet would have disabused you of that notion.

Robert

Robert Adsett said:

I think the temperatures for firing ceramics are likely incompatible with maintaining pn junctions

Yet it would seem a ceramic capacitor should exist in R/C of the PIOSC, how else could it maintain even 4.5% precision prior to software calibration up to 1% precision. 

There are IC with programmable capacitors, I always believed were ceramic. Perhaps they are being placed by robotic insertion into cutouts in the silicon die. There exists robotic surgery can stitch closed the skin of a grape these days.

BP101 said:

There exists robotic surgery can stitch closed the skin of a grape these days.

Such (may) prove true - but (only) when the "robot" accepts the "unaffordable/careless" insurance - presented in advance - by the (injured) grape...

I know of a good many applications which simply don't need a high level of precision to the clock. It's all relative: most I/O is either synchronous or extremely slow, and the point at which you need to guarantee drift is the point you would plan to use an external controlled oscillator anyway. Actually, when you look at LIN, the protocol goes to great lengths to synchronize unstable-clocked endpoints prior to transmission.

I've worked in three industries now: two of which have bigger problems with crystal fabrication in general and one of which was running to such an extreme of temperature you had to design-in oscillator drift from day1. Hence, as a general concept, I'm quite accepting of the RC based oscillator in favour of reduced component count.  

Annoyingly enough, for my current application, I need to run the Ethernet port: which it seems does need an external clock. This for me is a bigger annoyance, as I can guarantee the temperature of the circuit and could have probably got away with the RC. Still, the point at which I buy a single piece of silicon which covers 100% of my needs is the point at which I'm out of a job...

Mat

May I (despite the ban - especially due to the ban) note, *** LIKE ***

It is noted that, "Single piece of silicon - covering UNIVERSAL NEED (i.e. "Kitchen Sink")" appears "holy grail" of MCU vendors - and usually proves "highly compromised - border-line unusable!"     (see vendor's EEProm implementation, errata, restrictions... pardon (barf) bag (may) be required...)

Your "job status" appears (unlikely) to dissipate w/in the (near) future...    (hapless "grape" may be unable to "make such claim.")

cb1_mobile said:

Such (may) prove true - but (only) when the "robot" accepts the "unaffordable/careless" insurance - presented in advance - by the (injured) grape...

Help my grape has fallen down and can't get up, so many stitches in very fine skin outlawed opioids can no longer kill the pain "UCA" left in wake.   

BP101 said:

my grape has fallen down and can't get up

Somewhere - there (must) be an MCU APP - for just that...

Unfortunately - firm/I "stock" (most) every "cream" - known to man!    (results not (yet) to spec...although "your" 0-grav. may change that)

BP101 said:

Robert Adsett

I think the temperatures for firing ceramics are likely incompatible with maintaining pn junctions

Yet it would seem a ceramic capacitor should exist in R/C of the PIOSC, how else could it maintain even 4.5% precision prior to software calibration up to 1% precision. 

Note the highlighted key word in the specification

Robert

As cb1 says this deserves a like.

Mathew Maher said:

I know of a good many applications which simply don't need a high level of precision to the clock. It's all relative: most I/O is either synchronous or extremely slow, and the point at which you need to guarantee drift is the point you would plan to use an external controlled oscillator anyway.

And some of these are quite high volume.

Mathew Maher said:

Actually, when you look at LIN, the protocol goes to great lengths to synchronize unstable-clocked endpoints prior to transmission.

Yep, the entire point of LIN is to save $0.10 on a crystal or resonator.

Most communication protocols though need at least the accuracy of a resonator and many need a crystal. Some of the self clocking protocols might get away with less accuracy and stability but I haven't heard of them in ages. There's probably places that use them though.

Mathew Maher said:

I've worked in three industries now: two of which have bigger problems with crystal fabrication in general and one of which was running to such an extreme of temperature you had to design-in oscillator drift from day1

Out of curiosity, and you may not know, would a MEMS oscillator be better suited in those cases? I can think of reasons they might be more resilient but whether it's enough is another question. Last I looked you could even get programmable standalone MEMS oscillators.

Mathew Maher said:

This for me is a bigger annoyance, as I can guarantee the temperature of the circuit and could have probably got away with the RC.

I had the misfortune of working with a product where someone thought a non-temperature controller precision microprocessor oscillator was sufficient for UART communications. We ended up disassembling the product to figure out why we were having so many problems with it (that was one of them).

Mathew Maher said:

Still, the point at which I buy a single piece of silicon which covers 100% of my needs is the point at which I'm out of a job...

Heh...

Lots of reasons to think that won't happen anytime soon.

That and drag and drop development systems for non-trivial development.

Robert

Mathew Maher49 said:

no, but if you speak to a pharmacist and describe the problem, I'm sure theres some cream available...

Robert Adsett said:

Note the highlighted key word in the specification

So are you thinking the words factory calibration elude to there being any ceramic material in the RC? To me that means the oscillator silicon elements with an ceramic resonator & precision resistor. Back in the day (multilayer) ceramic caps did not exist so perhaps PIOSC is an RC resonator comprised of such materials even exceeding what used to be sold as external 3 leg device to oscillator circuit.

Again the PIOSC can drive the PLL and at 1% re-calibration (likely constrained) yet could not clock EMAC0 but is much more stable for a GPTM clock source than PLL 80-120Mhz SYSCLK. None of which could be clocked externally to provide EMAC0 clock, disable MOSC may force bypass PLL mode ? perhaps slow the ARM CPU to 25Mhz. PIOSC can then drive GPTM and other peripherals if not mistaken.

BP101 said:

Robert Adsett

Note the highlighted key word in the specification

So are you thinking the words factory calibration elude to there being any ceramic material in the RC?

What's it trying to avoid?

And no I think it means the oscillator is calibrated in some unnamed fashion. Uncalibrated performance would be significantly worse, there would otherwise be no reason for calibrating.

BP101 said:

Again the PIOSC can drive the PLL and at 1% re-calibration

At a specific temperature. They don't show the curve but I suspect that means the oscillator will actually fare worse over the temperature range. Certainly they provide no garantees beyond the calibration temperature.

There is no reason to use ceramics for RC and no reason to think that anyone has done so (and in this case we know it hasn't been done). Where ceramics would be useful is on the power inputs where they could make a big difference to decoupling and thus noise and maybe operating frequency. But that would also involve space and so might only be used in a fraction of the cases (although less capacitance would likely be needed to make a difference if it was internally placed rather than externally placed).

Robert

Robert Adsett said:

Certainly they provide no garantees beyond the calibration temperature.

Well it would seem PIOSC can be recalibrated via Tivaware at any time relative to variance in MCU temperature if so chosen, perhaps restrained from B2B writes or so many CLK cycles. That kind of algorithm would then seem to hold 1% across a large temperature range. I might try to write such code after thinking about purpose of PIOSC for several GPTM.

Robert Adsett said:

There is no reason to use ceramics for RC and no reason to think that anyone has done so

It would seem the most available stable resource for such high frequency, next guess likely some kind of metal film yet not Si MOS, so what's wrong with impregnating ceramic chip on/in the die if metal film RC. Seem to recall metal film caps are not very stable with high frequency oscillators above 4Mhz. 

Robert Adsett said:

Where ceramics would be useful is on the power inputs where they could make a big difference to decoupling

Yet would add to production cost and decoupling capacitance value is very specific to the application of input signal.   

BP101 said:

so what's wrong with impregnating ceramic chip on/in the die

The first problem that comes to mind is processing temperature, there may be chemical incompatibilities as well.

BP101 said:

Robert Adsett

Where ceramics would be useful is on the power inputs where they could make a big difference to decoupling

Yet would add to production cost and decoupling capacitance value is very specific to the application of input signal.   

Not true. Decoupling does not depend on the input signal. It does depend on the edge rate but that is independent of input signal and clock frequency.

It's a valuable enough addition that some high end microprocessors include them on their package.

From EE-Times Asia http://archive.eetasia.com/www.eetasia.com/ART_8800712242_480200_TA_3b9f2117.HTM Whether you consider that a CPU or a complex PCB sub-assembly is a POV question. It comes from the manufacturer like that so I'd call it a CPU.

Robert

BP101 said:

Robert Adsett

There is no reason to use ceramics for RC and no reason to think that anyone has done so

It would seem the most available stable resource for such high frequency

The most stable readily available frequency sources would be an OCXO (There are more stable sources but they're starting to get exotic and expensive), next would be crystal, MEMS oscillators, then resonator. After that you can consider RC.

However, crystals are inexpensive and MEMS are catching up in cost while matching (or close to) the crystal spec while being easier to use in circuit and some are even programmable.

Robert

@ Robert,

Crack staff (those still here/somewhat conscious (confirmed via "occasional twitch")) and I LOVE that great drawing.

NOT "too far" from our new, 6 FET (3x Half-Bridge) package - which employs similar techniques to accept HIGH Currents - while minimizing (and effectively dispersing) heat from the (vulnerable) FET die.

Novel & sound "techniques" - as w/"general forum problem solution METHODS" may prove "so good" as to enjoy (both) a LONG & EXPANDED/DIVERSE LIFE!     (i.e. Use across a multiple spectrum of applications...HEAT remains a powerful & most persistent ENEMY!)      Thanks for this...

Robert Adsett said:

Decoupling does not depend on the input signal. It does depend on the edge rate but that is independent of input signal and clock frequency

To funny, your talking about the DC power buss and I'm thinking more like MCU peripheral signal pins being decoupled internal ESD protection diodes. Intel has placed external decoupling caps on BGA processors attached to a ceramic substrate (PCB) for few decades. They must reflow the BGA to substrate in controlled temperature RAMP profile using a very specific solder paste.

Robert Adsett said:

The first problem that comes to mind is processing temperature

Not if the cold ceramic chip was simply wired into the silicon circuit and how else do you think the C part of RC is embedded into the PIOSC silicon circuit at present?

BP101 said:

Robert Adsett

Decoupling does not depend on the input signal. It does depend on the edge rate but that is independent of input signal and clock frequency

To funny, your talking about the DC power buss and I'm thinking more like MCU peripheral signal pins being decoupled internal ESD protection diodes.

That wouldn't be called decoupling. That appears to be your own unique terminology.

BP101 said:

Not if the cold ceramic chip was simply wired into the silicon circuit and how else do you think the C part of RC is embedded into the PIOSC silicon circuit at present?

The way they have always been. They are formed directly in the Si using the same processes that are used to make transistors, resistors and connections. SRAM, DRAM, EPROM, EEPROM and Flash all depend on capacitors formed in the silicon.

Robert

Note - vaunted "forum upgrade" becomes confounded by "commas" w/in Tag area.      And I (still) cannot find LIKE...

Robert Adsett said:

That wouldn't be called decoupling

Robert Adsett said:

They are formed directly in the Si using the same processes that are used to make transistors

According to your earlier post it would be far to hot for a ceramic capacitor as part of the die and you challenged my point of a ceramic being part of the RC of the PIOSC clock. Not sure what you were getting at about firing ceramic in the silicon and BTW ceramic resonators are far more temperature stable than XTALS ever were. Often was used in 455kHz IF of FM receivers for that exact reason, less drift than XTAL.

I recall when 3 leg ceramic resonators first hit the market around 1985 but there are a few different types even one with 2 legs and a tuning fork of all things, perhaps less stable than XTAL. Still have a few  of each type floating around in the XTAL bin.

BP101 said:

Robert Adsett

That wouldn't be called decoupling

What else do you think would be at the ESD diode on each pin other than a ceramic decoupling capacitor.

On-chip?

Usually nothing. In some cases there may be resistors in parallel or maybe some sort of active clamping. There will of course be parasitic capacitance. I haven't seen anyone add EMC filter caps on chip but I suppose it could be done.

BP101 said:

Not sure what you were getting at about firing ceramic in the silicon and BTW ceramic resonators are far more temperature stable than XTALS ever were.

BP101 said:

Robert Adsett

They are formed directly in the Si using the same processes that are used to make transistors

According to your earlier post it would be far to hot for a ceramic capacitor as part of the die and you challenged my point of a ceramic being part of the RC of the PIOSC clock. Not sure what you were getting at about firing ceramic in the silicon

No I said that the processing temperature for ceramic was likely too hot to be compatible with IC formation. Ceramics are fired at high temperatures. This is likely to affect the dopant profile in the silicon. There's also the issue of chemical and mechanical compatibility and of integrating screen printing into the process.  These may be surmountable but no one appears to have done so, which suggests it's not simple.

BP101 said:

BTW ceramic resonators are far more temperature stable than XTALS ever were.

Got a reference? I don't recall seeing that anywhere and the spec sheets I've seen indicate a temperature stability for resonators of on the order of 0.1% while for crystals it's on the order of 20ppm. Watch crystals are worse than standard high frequency crystals at 200ppm or so.

Robert

Robert Adsett said:

 These may be surmountable but no one appears to have done so, which suggests it's not simple.

Well it seems that is not the case at all since the PIOSC uses and RC and again metal foil/film capacitor would seem a bad choice @16Mhz and still be called a precision oscillator. Perhaps the LFOSC could get away with a metal foil/film cap. Yet the robot need only a few XYZ coordinates to place ceramic cap on the die plate area and weld it to contact pads on the die, not the pin. It would seem extremely difficult for human even under 16x diopter magnification to preform such a task though easy task for a surgical robot.

The issue of BGA DC bus caps brings in core voltage requirement, seemingly makes the cap to large to place inside the die plate.

Robert Adsett said:

I haven't seen anyone add EMC filter caps on chip but I suppose it could be done.

I think on that we both agree and my have misunderstood each others meaning for placing a ceramic capacitor inside the die versus outside for DC bus decoupling.  It is recommended to decouple almost every external GPIO signal with a ceramic capacitor near the MCU pin as possible, not always the case but often is required depending on the signal purpose. While PWM drive signals it is more common to capacitive decouple at the HVIC far away from the MCU pin and add pull down resistors near the MCU pins.

Getting back to the PIOSC clock source under pressure; it can be used as the ADC clock source but seemingly @1Mhz SPS when the PLL is being bypassed using an external oscillator versus MOSC. It seems the original poster has no further interest in pursuing TM4C129x MCU though I would suggest an (external carrier) typically shields silicon devices from excessive pressure or even heat.

BP101 said:

Robert Adsett

 These may be surmountable but no one appears to have done so, which suggests it's not simple.

Well it seems that is not the case at all since the PIOSC uses and RC

As I earlier noted, the existence of the PIOSC does not suggest the use of ceramic capacitors.

BP101 said:

Robert Adsett

I haven't seen anyone add EMC filter caps on chip but I suppose it could be done.

I think on that we both agree 

Nope.

BP101 said:

It is recommended to decouple almost every external GPIO signal with a ceramic capacitor

Non-sequiter. You can use your own terminology, but don't expect anyone else to understand you.

Robert

Robert Adsett said:

As I earlier noted, the existence of the PIOSC does not suggest the use of ceramic capacitors.

I believe ceramic would be the most logical choice and you have yet to suggest what type it would be otherwise and keep discounting ceramic the candidate. At least I suggested other types and doubt poly or Mylar would be suitable for 16Mhz and maintain 4.5%. BTW for PIOSC recalibrate @1% to current MCU temperature it must be calibrated (trimmed) against 32kHz HIB clock if one exists. I can't seem to even find Tivaware calibrate function (timer.c) but it seems there is a SYSCTRL register update that must take place.

Robert Adsett said:

Non-sequiter. You can use your own terminology, but don't expect anyone else to understand you

That is not my terminology it comes straight from several TIDA projects and you also left out quote mentions PWM driven HVIC at end of GPIO ports. Most all GPIO ports connect to some outside control, often inject noise on the control signal in some way or another must be decoupled to ground via a ceramic capacitor. Those who invest in TI resource development kits that deal with 24v and above voltages driving inverters and power supplies have full grasp how decoupling spikes from GPIO pins before they enter the MCU stop mayhem.

Mon Ami,

Have you not invested sufficient "time/effort" into the (further) beating of this "already dead" horse?    (design implementation of PIOSC)

Neither you, original poster, Robert nor I can influence/impact (at all) this "long completed" PIOSC design!    It simply, "Is what it is."

Is not the (glue factory's) prescribed, "removal of the carcass" being impeded - by your on-going attempts to "re-animate?"     One senses that further protest may force the delivery of the carcass - instead - to the "Dead FET Burial Ground" - (your backyard) - IIRC...

BP101 said:

Robert Adsett

As I earlier noted, the existence of the PIOSC does not suggest the use of ceramic capacitors.

I believe ceramic would be the most logical choice and you have yet to suggest what type it would be otherwise

Oh but I did, if you check back you will say that I said they were built on the Si in the same fashion that resistors, transistors and connections were. I even worked out a cost estimate of making DRAM using discrete capacitors.

For more explicit information you can check wiki

https://en.wikipedia.org/wiki/Integrated_circuit

And their article on DRAM has a nice illustration of a capacitor transistor combination used to make DRAM cells (the structure used today are more sophisticated).

https://en.wikipedia.org/wiki/Dynamic_random-access_memory

BP101 said:

That is not my terminology it comes straight from several TIDA projects

I have no idea what a TIDA project is and a quick search just leads to Tidal power projects. So whatever these are they are either uncommon or referred to by another name.

Robert

Robert Adsett said:

And their article on DRAM has a nice illustration of a capacitor transistor combination

That is a memory cell :The capacitor in the stacked capacitor scheme is constructed above the surface of the substrate.The capacitor is constructed from an oxide-nitride-oxide (ONO) dielectric sandwiched in between two layers of polysilicon plates (the top plate is shared by all DRAM cells in an IC), and its shape can be a rectangle, a cylinder, or some other more complex shape

That doesn't suggest the same process is being used for the PIOS RC and there is no indication what frequency ONO dielectric is even capable of. DRAM as you know has typically slow access rate, requires refresh cycles, wait states to keep the space charge barrier region in each cell charged or data is lost. Yet notice ONO dielectric is constructed above the surface where a ceramic chip can just as easily be placed on pads sandwiched between two layers of poly silicon plates. No telling if the ONO dielectric process is stable enough for time constants at 16mHz, off hand I would bet not at all and perhaps as you believe some other process similar to ONO is being used to form high frequency capacitor.

Robert Adsett said:

I have no idea what a TIDA project

Seriously you don't recall I recently posted 16KW IGBT motor driver kit link TIDA-00195 in a comment to you, decouples most all MCU GPIO ports.  TIDA-00778 mentions decoupling caps near MCU often called bypass caps when placed near power pins of chip. If you get the TI news letter emailed (TI profile preferences) many development kits and different projects are in the limelight, often weekly. The latest this week is dime sized DC/DC inverter (36v-16v) input bucks down to 12v @6amps output using GaN FETS with integrated gate drivers.

Good read of ceramic dielectrics can't say I was 100% up to date on the tpoic;

BME nickel electrodes & ceramic (CaZrO3)   dielectric become centered at 1550*F, obviously liquids. Seemingly the PME (Ag/Pd) electrode also refer to ONO (BNT) type dielectric and have similar fire temps?

However I was referring to the metal deposit between the PME/BME electrodes being the same as the ceramic capacitor and not the dielectric. Though it seems the electrodes + dielectric connection methods produce the stability and precision of CaZr03 type dielectrics.

Perhaps TI could give a little more detail in datasheet as to what gives the PIOSC so much precision...

http://www.kemet.com/Lists/TechnicalArticles/Attachments/40/2013-03%20CARTS%20-%20BME%20Ceramic%20Capacitors%20for%20High-Reliability%20Applications.pdf

BP101 said:

...could give a little more detail in datasheet as to what gives the PIOSC so much precision...

Might that "lack of detail" (is not "more" detail an exaggeration) - possibly suggest - such (unsupported) claim (precision) stems from, "Marketing?"     (such does occur - via multiple vendors...)

While you've seized (only) upon use of a certain type cap. - other factors: (reduction of oscillator current; strategic placement (possibly isolated/physically guard-banded/secure); tightened voltage control) all may lead to use of such term.   (precision)      Is it not, "in the realm" that certain (perhaps several) such techniques are vendor "proprietary" - thus not destined for such public disclosure.

Anyway (again) "All the, King's horsemen" could not alter PIOSC construction (now)!      Again - "It IS what it is..."     (thus endless, on-going pursuit - rings w/out (much) purpose...)

If one (really) sought to, "Judge precision" would not frequency measurement - over a wide range of: "temperature, voltage, product lots and aging" - provide the (required) independent confirmation?    

It is possible that use of "precision" was used "comparatively" (i.e. comparing/contrasting vendor's internal oscillator performance vs. "others' norm"!)       Such (if true) may have led to your, "raised expectations."     (which may - or may not - have been met and/or delivered...)

Might the "claimed (yet unsupported) forum upgrade" - have yielded such, "precision?"