Tool/software: TI-RTOS
hi Champs,
I ran TM4c123-EK TI-RTOS example code. I write slave address = 0x50 which didn't exist. On I2C bus, it generates address NACK and sent first byte out. in first I2C transfer, TM4C123 issue STOP bit and it looks like generate automatically. However, it didn't issue STOP bit in second transmission. SCL keep low after second transmission finished. Why 123 didn't issue STOP bit if it got address nack ? Why it still sent out 1 byte data. Why 123 didn't issued a STOP bit after second transaction?
I checked i2cTiva.c. there is a else loop which write
if (errStatus & (I2C_MASTER_ERR_ARB_LOST | I2C_MASTER_ERR_ADDR_ACK)) { I2CTiva_completeTransfer((I2C_Handle) arg);
}
I just wonder that why 123 got address nack and still need to complete transfer ? Could you please tell me why our example write this condition ? thanks!
1. first transaction
2. second transaction
3. whole transaction