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TM4C1294KCPDT: Could we control the interval of SPI's clock?

Part Number: TM4C1294KCPDT

Dears:

We are using the SSI code of TI to read data from SPI Flash, and the code as below picture:

During our reading we find the SPI's clk will change to bigger interval of clock occasionally.

Could we control the interval of SPI's clock or avoid the issue?

Pls. kindly help to give some advice.

Thanks a lot!

Best regards

Luck Wu

  • The functions you have chosen always wait for successful completion before returning. In this case the call to SSIDataPut() returns quickly as it puts data into the FIFO to be transmitted. The function SSIDataGet() will wait until the previous transmission (and reception) have completed before returning. That means there is a delay before the next value to transmit gets loaded in the FIFO. There are many ways to keep the transmit FIFO from emptying before the last value is transmitted.
    1. You can call SSIDataPut() in a loop like now, but read the data in an interrupt routine, or use the uDMA.
    2. You can call SSIDataPut() in an outer loop, and then call SSIDataGetNonBlocking() in an inner loop as long as it reads data. You will need to keep track of how many values have been read because you will be finished "Putting" the data but still have 16 more pieces of data to "Get".
    3. If the amount of data is less than the buffer size (16 items) you can call SSIDataPut() in one loop, and then call SSIDataGet() in a subsequent loop.
  • @ Bob,

    Truly "inspired!"     So much so that a "brand new" check box is suggested: ... ... ***  SUPER  LIKE  ***.

    Vendor agents must service many - the time/effort presented here registers as,  "Off the chart"  helpful.    

    Great job - this should be promoted to, "Easily Found" status - rather than being permitted to "rotate away" (from forum's front page)  into forum oblivion...

    (of course - crack staff has "Copy/Pasted" your response - now appearing "Page 1" - our  "SPI Peripheral Notebook."      (such positive & timely action trumps (later) search ... (maybe) find...)

  • Dear Bob:

    Thanks for your suggestions, and we need check the issue with more information again.

    Why between the Byte and Byte the width has differenc?

    For example, we need the width is same when we are reading the 1000 times for loop.

    Why the width of A and B is different, however the code is the same code.

    Btw, could you kindly help to provide the example code of DMA or other exaples? We want to test it.

    Many thanks, pls. help us!

    BR.

    Luck Wu

  • I suspect the difference has to do with how the software loop of your original example coincides with the completion of the SPI transmission. Have you been able to implement one of the suggestions I made above to keep the SSI TX FIFO full until the end of the data transmission?
  • Hi Bob:
    We want to try testing, could you kindly help to provide the example code of DMA or other examples?
    Thanks a lot!

    BR.
    Luck Wu
  • Hi Luck,

    Are you in SPO=1 and SPH=0 mode?

    Do you have the scope cap of the FSS (chip select) pin?

    The reason I'm asking for your SPI mode and scope cap for the FSS pin is because by design the FSS will go high during idle cycle even during continuous transfer. The wider SPICLK in your capture indicates the SPI is in Idle state. Please refer to the below datasheet notes. 

    In the case of a single word transmission, after all bits of the data word are transferred, the SSInFss

    line is returned to its idle High state one SSInClk period after the last bit has been captured.

    However, in the case of continuous back-to-back transmissions, the SSInFss signal must be pulsed

    High between each data word transfer because the slave select pin freezes the data in its serial

    peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master

    device must raise the SSInFss pin of the slave device between each data transfer to enable the

    serial peripheral data write. On completion of the continuous transfer, the SSInFss pin is returned

    to its idle state one SSInClk period after the last bit has been captured.