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TM4C1294NCPDT: What are the threshold voltages used for the timing measurements in the Electrical Characteristics section of the datasheet?

Part Number: TM4C1294NCPDT

I need to know this in order to check the timings of an EPI bus interface to an external device.  I will be using HyperLynx to compare the timings with a reference load to those with my actual PCB and load, to work out timing correction figures.

The TM4C1294NCPDT datasheet provides the load conditions for the timing measurements (e.g. 30pF to ground for EPI signals), but doesn't say explicitly what the voltage thresholds are that are used to define the input and output timings.

For example, parameter E30, Falling clock edge to output valid for EPI General-Purpose Interface, is 4ns max: was this measured by looking at the times when the signals pass through 50% of VDD, or was it measured using 35% of VDD for falling edges and 65% of VDD for rising edges (the input thresholds for Fast GPIO pins)?  Or something else?

Proper signal integrity analysis requires that I take account of any difference between the thresholds used for the datasheet timings and the thresholds of the actual devices used on my board.

Thanks,

Michael

  • As it is suspected that you "know" - your pcb interconnect routings, board quality, impedance-matching ... ALL will impact your signal timings.

    May I note - should the (slight) variance in "threshold levels" prove a "game-changer" - it is my (and my firm's) experience that you are, "courting timing disaster."    (if not immediately - then under varying conditions of voltage, temperature and component aging/process variations...)

    You (may) succeed - but "Risk-Reward" - at least to me - seems "Not high in your favor!"

  • The timings are based on 20% / 80% of VDD.
  • Indeed 20%/80% of Signal Max (I'm not so sure as to VDD) is a known, popular and reasonable standard.
    That said - might you comment upon the, "Slight Variation imposed by different reference levels" - exercising impact upon a design?

    As earlier noted - should a design implementation "cut things that closely" - the design risk proves "unsuitable" for many...
  • HyperLynx simulation shows that a GPIO pin set to 2mA drive strength, driving a falling edge into the reference 30pF load, can take up to 6.9ns longer to reach the 20% threshold than the 50% threshold - a not insignificant effect.

  • I'm unaware of "50% threshold level" being chosen as a, "normal/customary" standard.     (20/80 mainly - 10/90 2nd - dominate - and their  timing "delta" is far less - thus you've "weighed" your finding.)

    And - are not the "Vendor Supplied Threshold Levels" - "Typical Values" which surely vary - and be impacted by temperature, process variation, other factors?      You've been (notably) silent - in this regard - have you not?

    That 2mA drive strength seems "light" to me - higher drive further erodes the "impact" of such "thresholds."     Firm/I work  reasonably regularly w/VCs - they almost certainly would, "Register concern" when timings are, "cut so close!"       (my objective is to "offer assistance" - the decision is yours...I've registered my (and others') alarm!)