I need to know this in order to check the timings of an EPI bus interface to an external device. I will be using HyperLynx to compare the timings with a reference load to those with my actual PCB and load, to work out timing correction figures.
The TM4C1294NCPDT datasheet provides the load conditions for the timing measurements (e.g. 30pF to ground for EPI signals), but doesn't say explicitly what the voltage thresholds are that are used to define the input and output timings.
For example, parameter E30, Falling clock edge to output valid for EPI General-Purpose Interface, is 4ns max: was this measured by looking at the times when the signals pass through 50% of VDD, or was it measured using 35% of VDD for falling edges and 65% of VDD for rising edges (the input thresholds for Fast GPIO pins)? Or something else?
Proper signal integrity analysis requires that I take account of any difference between the thresholds used for the datasheet timings and the thresholds of the actual devices used on my board.
Thanks,
Michael