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TM4C129XNCZAD: Max. IO voltage, confusing datasheet

Sven Probst
Expert 1630 points
Part Number: TM4C129XNCZAD
Other Parts Discussed in Thread: SN74CBTLV1G125

I'm confused about the ESD structure and the usage of GPIOs and the Ref+ Input, when the device is unpowered. I'm referring to the device datasheet as of June 2014

The Maximum ratings (Table 32-1) state:

VIN_GPIO | Input voltage | -0.3 | 4 | V

Table 32-7. "Recommended FAST GPIO Pad Operating Conditions":

VIH | Fast GPIO high-level input voltage | 0.65 * VDD | - | 4 | V

Both specifications are independent of VDD, thus no clamping diode to VDD can be assumed.

But Table 32-37. "Non-Power I/O Pad Voltage/Current Characteristics" states

VIO | IO pad voltage limits if voltage protected | -0.3 | VDD | VDD+0.3 | V

This specification is consistent with figure 32-17. "ESD Protection for Non-Power Pins (Except WAKE Signal)", but in contrast to the other two tables.

Could somebody clarify the issue?

I have to provide an external 3.3V reference voltage to the device. Are there any recommendations how to do it?

  • 0
    TI__Guru 72500 points
    The absolute maximum input voltage of table 32-1, 4 V, is the largest voltage that can be applied before damage may occur. If you apply that voltage to an unpowered part, you will violate the specification of table 32-37 which states you must limit the maximum positive injection current to 2mA. In short, the 4V absolute limit can only be approached when VDD is also near 4V. There is a clamping diode to VDD as shown in figure 32-17.

    Is he reference for Vrefa+? It is best if the 3.3V reference to Vrefa+ not be applied when the device is unpowered. Otherwise you must add 1.7K of series resistance which can drop your reference voltage by 750mV. Not a good solution.
  • 0 in reply to Bob Crosby
    Expert 1630 points

    Dear Mr. Crosby,

    thank you for clarifying my question.
    It would be convenient to the reader to glue those tables together as TI does e.g. for all standard logic ICs known to me. There seems to be the simple rule: clamping diode to VCC <=> Input max. rating expressed as VCC+x; Zener like ESD protection <=> absolute number.
    Now these two tables are 32 pages separated and the second is easily overlooked.
    Your explanation stays still inconsistent to the recommended operating conditions: VDD max. = 3.63V => max. input voltage = 3.93V != 4V according to Table 32-7 "Recommended FAST GPIO Pad Operating Conditions".
    Could you please cross-check and ask for improvement of the datasheet?

    W.r.t. the reference: I'm going to let the µC switch the 5V rail, thus the 5V supplied reference device will also get switched.

    Thank you in advance!

  • 0 in reply to Sven Probst
    TI__Guru 72500 points
    Hello Mr. Probst,
    You make an excellent suggestion. I will forward on your recommendation for improvement to our datasheets.
  • 0 in reply to Sven Probst
    Guru 117850 points

    Sven Probst said:
    I'm going to let the µC switch the 5V rail,

    Feel your pain - you should know that "Marketing" often "cracks the whip" upon Tech Writers - and the MCU manual DOES exceed 1,000 pages.    (and NEVER is "really" done!)

    Now to your quote - just to be sure (NO offense intended) - it is clear that your MCU  "CAN"  switch the 5V rail OFF - but does the removal of that 5V rail (then) "remove the 3V3" (suspected to spring from the 5V rail)  from the MCU?    If so - how does the MCU (then) "switch that 5V rail back on?"      (asked as we have - more than once - observed (even) large clients - becoming so entrapped.)

  • 0 in reply to cb1_mobile
    Expert 1630 points

    Thank you for very much your remark. It's good to feel the support of people in this forum.
    Indeed in the original design the 3.3V was derived from the 5V rail. I had to use the next upper rail, which is 18V. Unfortunately the buck-converter lost efficiency, but that is not a main concern for this design.
    Maybe TI could consider a different ESD structure or spend a buffer for analog inputs. Now there is discrepancy: The ADC should be fed by a low impedance source but you have to apply current limiting resistors to reach <2mA (e.g. with external sensors you can't switch off). Getting Schottky diodes for external clamping with less than Vf = 300mV is also no simple task. External buffers are overkill. If you have any hint for a generic solution, please let me know.
    Please let me also know, if following is alright:
    The ADC impedance is dominated by capacitor switching. In my case the signal I want to measure is slow, thus a low sampling rate is sufficient. Is it possible to connect the signal via - let's say - 10k to the ADC input and placing an e.g. 100nF capacitor from the ADC input to GND (to get the dynamic impedance low)? I want to reach close to 12bit resolution at 100 samples/s.

  • 0 in reply to Sven Probst
    Guru 117850 points

    I'm fearful that your 10K R - in series w/the ADC input - even w/100nF cap (very close) to the ADC input - (may) prove too high.    (yet I'd deploy it - (test/measure) -  that 100nF cap (may) save you.)     And - under the conflicting demands placed by the MCU - and your unique design - you are placed in a difficult position.

    While you note that  imposing buffers between your external sensors:  (which can't switch off) and the MCU  "prove overkill" - they DO appear - "best able"  - to meet your (unique, even conflicting) circuit needs.

    I would add that - to my best knowledge - no "Mixed Signal, MCU" can (really) achieve 12 bit accuracy.     Our findings - across multiple ARM vendors (including Cortex M4s & M7s) reveals the 3 lsb as "jittering/suspect."     The quality of your "Reference" - applied to VDDA+  - is of great importance - as well.

    Your concern for - and great "Attention to Detail" - bodes well for your project's success...

  • 0 in reply to cb1_mobile
    Expert 1630 points

    I just remembered a quite universal problem solver: SN74CBTLV1G125

    This bus switch (Ron <=15Ohms) can e.g. isolate the processor pins from external signals when being disabled or un-powered with an Ioff specification of 10µA. I just checked it in the lab and it really works: When being un-powered you can apply 4V to its channel pins without any significant current flowing.

  • 0 in reply to Sven Probst
    Guru 117850 points

    Agreed - this chip is quite a "problem solver."

    Question remains - my review of the datasheet reveals (direct quote follows):
    "The switch is disabled when the output–enable (OE) input is high."

    As you note the desire to "Isolate the processor pins from external signals (while) "un-powered" - and pin (OE) must be driven to 2V or above to achieve such isolation - that (OE) signal voltage must be applied from a "Non-MCU" source - is that not so?

    And - if that's true - as the MCU appears NOT the controlling source - how is pin (OE) switched when the output is to be enabled?      (it is suspected that a small signal transistor - set as open collector (inverter) - can be imposed between the MCU's GPIO & "solver's" pin (OE) - enabling the MCU to "Control (OE)" - once the MCU is powered-up.)     In this manner - the "external circuit" (alone) provides the voltage to "Disable the switch" - and (only when powered) the MCU may, "Enable or Disable" the switch...

  • 0 in reply to cb1_mobile
    Expert 1630 points
    Please have a look at the further lines of the data sheet:
    "This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging
    current will not backflow through the device when it is powered down. The device has isolation during power off."
    And further:
    "To ensure the high-impedance state during power up or power down, nOE should be tied to VCC through a pullup
    resistor;"

    Thus the SN74CBTLV1G125 can be powered with the same supply as the processor. The device stays isolating with a pull up at nOE as mentioned in the data sheet. The nOE can then be driven by a processor pin (which is high impedance during power on until being configured) or simply by a power good signal. I'm somewhat unsure if VDD3ON mode of the hilbernation module might need special consideration, because "The first mechanism (VDD3ON mode) uses internal switches to control power to the Cortex-M4F as well as to
    most analog and digital functions while retaining I/O pin power" (processor data sheet). Thus the processor pin controlling nOE could keep the SN74CBTLV1G125 on, while analog functions are switched off. This could be an issue e.g. with the external Vrefa+ ?

    I like the power good signal solution best for now, because it is intrinsically safe (without software intervention), it saves a processor pin, it is already available from the buck converter (might cost a BSS138 for inversion).

    Please let me know, if I overlooked something ...
  • 0 in reply to Sven Probst
    Guru 117850 points

    May I disagree?     And I (did) "have a look"  (even) at those further lines - w/in the data sheet.

    Let's return to that Switch data-sheet.    "The switch is disabled when the output–enable (OE) input is high."

    Now you claim that Switch IC,  "Can be powered with the same supply as the processor."     Thus - when power is REMOVED from the MCU - and that MCU power is to supply (OE) - how (then) does (OE) maintain its "high input?"     Clearly - it cannot!

    You may note - that in the final paragraph of my writing - I suggested that such "Voltage to (OE)" be supplied from a "NON-MCU" Source - as the MCU could not maintain (OE) high - when unpowered!

    I do not see any fault in such logic!      In fact - I will (now) make the case for this method's (OE held high) "superiority!"  

    Your (new) quote from the Switch Datasheet notes,  "The device has isolation during power off."    What happened to "disabled?"    Why the unexplained change?    (note: this asked of vendor - Not of you!)     Has "Isolation during Power Off" been fully/properly defined?    Does it mean "ONLY" removing power from the Switch's "VDD" pin?     Is that "isolation" as strong/solid and ROBUST - as "disabled"  - achieved via (OE) pulled high?

    Why have differing terms been employed - if their meaning is "the same?     (having been to Engineering & Law school - words/phrases/clauses ... have meaning ... and  neither, "Isolation during power off" or "DISABLE" (to my mind) have been -  fully/properly  detailed/disclosed...)      And - does not the term "Disabled" - appear FAR STRONGER,  MORE IMPACTFUL - than  the  vague/lesser, "has isolation?"    I want your design to succeed - thus I would opt for  (some) "Vendor Clarity of terms" - and comply w/  "Disabled's" circuit requirements - to be (most) safe.      

    May it be noted that your Thread's Subject line noted,  "MCU's Datasheet Confusion?"     Might that "confusion" - have flowed to your Switch IC's datasheet  - as well?     (via same vendor!)

    The chip you've deployed (or are about to) proves (very) well suited to your task.    (and firm/I will "steal the application" - yet we WILL drive Switch (OE) - from a NON-MCU Source - when the MCU is de-powered.)    (to best insure the "full/proper  Switch DISABLE!.")

  • 0 in reply to cb1_mobile
    Expert 1630 points
    Sorry, it was not my intention to express that you didn't read the further lines - no offense!

    I'm not going to discuss the meaning of words in a language not being my mother tongue. I.M.H.O. the data sheet sounds very clear and there is clear information what isolation means: Ioff<10µA@VCC = 0, VI or VO = 0 to 3.6 V.
    For the application of protecting the µC pins that is good enough, and we used the device for similar applications in the past successfully. If you want to achieve less than 10µA you have to use the solution you explained.
    You are right that the time interval of powering the µC off needs special consideration. There are I.M.H.O. two cases:
    1. The external signal is limited to (VDD Brown-Out Reset Threshold) 2.77V+0.3V max. ==> Then a µC output connected to the nOE pin and a pull-up to Vcc (same for µC and bus switch) do the job: As long as the µC is not in Reset, the bus switch stays e.g. on. When µC gets reset, the pin gets high Z thus the pull-up disables the bus switch (as described in its data sheet).
    2. The external signal is higher than 3.07V and <= Vcc,nom ==> we need a good voltage monitor or a µC internal comparator to switch off the bus switch already when Vcc falls below Vcc,nom-0.3V (or a similar approach).
    In our case your solution does not fit, because there is simply no supply available in some cases (some µC pins are connected to a pcb external 3.3V UART communication).
    It was not the intention of my original mentioning of the bus switch to provide a full solution. But the Ioff specification, its low price and its compact package made me feel it could be interesting to other developers, too.
  • 0 in reply to Sven Probst
    Guru 117850 points

    Thank you for (another) well argued & clear writing - much appreciated.     I find your ability to, "Delve deeply into the datasheet - and harvest data from different  datasheet segments/locations (even unexpected ones) - both notable & effective."

    I do stand by the use of  "different terms" by the chip vendor - to (apparently) describe the same performance parameter - unsettling/unwanted - even "confusing."

    Now you do say that (my) solution,  "Does not fit, because there is simply, "No supply available in some cases."     Yet - was it not reported (earlier) - that this "Switch IC" is being deployed - because your Sensors remain powered  "while your MCU is de-powered?     [your post here - 13 Mar - 5:34 p.m. noted,  (e.g. with external sensors you can't switch off)]        That sensor supply then  MUST be available - must it not?     Note too - it is the (unwanted) "signal pass thru" - from those STILL POWERED Sensors - which you (properly) seek to BLOCK from the MCU...

    I completely agree w/you - your presentation of this "Switch IC" - even outside/beyond its "Protect MCU mode" - may prove of great value to many here.    

    Thank you for presenting this (little known) solution - yours truly is evidence of the,  "Ideal Forum Spirit..."

  • 0 in reply to cb1_mobile
    Expert 1630 points
    I have to admit that my posts are related to different interfaces of our current project. The sensors have power as you mentioned I could use, but the UART communication is connected to modules which get their power directly from the 48V rail on a different way. Especially during commissioning those could be powered while the whole µC pcb has no power connection.