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TM4C129XNCZAD: Unable to measure 120MHz system clock at PQ4

Chee Chein Wong
Prodigy 230 points
Part Number: TM4C129XNCZAD

Hi,

I configured my TM4C129XNCZAD to run at 120MHz and trying to output this clock speed through PQ4. However, I am not able to get it even through the settings of the register are correct. The maximum frequency I can see is 60MHz. I am just wondering if this is the limit of the GPIO speed?

  • 0
    Guru 117850 points

    It is believed that there is - at minimum - at least one "Divide by 2" circuit imposed between System Clock and Signal Output.    I would add - that the ability of the MCU's output stage - is (unlikely) to support 120MHz.    (and such holds true for other vendor devices - too.)

    Configuring the MCU's Timer as PWM Output - produces the highest (usable) programmable frequency output - although I doubt that it can reach your reported 60MHz.    (I'd bet that 30MHz (div by 4) is the highest frequency which a Timer generated PWM Output can sustain.)

  • 0
    Genius 3850 points

    You should talk to some very "seasoned" programmers here who could only get a few MHz output  - you got it to 60Mhz. 10x better than they could. I will link in their posts here later.

    As to your question, try to see if the chip support outputting master clocks and go from there.

  • 0 in reply to Danny F
    Guru 117850 points

    In defense of those programmers you reference (I don't believe that I fell among that group) their,  "Maximum Freq. GPIO Outputs" were constrained by their "likely/rightful" desire to produce:

    • a (reasonably) shaped/level output
    • WHILE maintaining the MCU's capability to service normal/customary MCU tasks

    Is not the (real) reason for the current poster's, "High Speed, Output Achievement"  the result of  his exploitation of a, "Specialized HW-only mechanism" - present w/in the '129 family devices?   (and not w/in '123.)

    The "seasoned" approach you identified, "DID tease out" the fastest GPIO pin toggle, while employing, "Inescapable, cascaded, ASM, "Bit ON - Bit OFF" instructions" - which "disallowed" Real-World MCU functionality.     

    Might it be that (both) your method - and those of  herein referenced others - both have their place?      (i.e. Different goals (usually) require (somewhat) differing methods...)    

  • 0 in reply to cb1_mobile
    Prodigy 230 points
    Hi,

    I am actually trying to use the CLKOUT feature to verified the system frequency I have configured. I would be happy to agree with you there is an "divide by 2" circuit imposed between the Sytem Clock and Signal Output. However, I will be more convinced if someone from TI could help to verified this believe.
  • 0 in reply to Chee Chein Wong
    Guru 117850 points

    Thank you - appreciated.

    You may note 2 key facts:

    • this vendor - not I - marked my earlier posting as, "Suggested Answer."     (never do I "Vote for myself")
    • a more general approach to, "Ease the Measurement" of System Clock (applicable to '123 as well as '129) is to employ (any) MCU Timer w/in its, "PWM output Mode" - to provide a, "Frequency Divided" - highly accurate "replica" of the System Clock.     Importantly - as this signal is lower in frequency (yet the division factor is integral & known) such method imposes no (added/unwanted) loading upon the System Clock hardware - which may negatively impact such frequency measure.

    This "more general" measurement technique may be extended to ARM MCUs from "others" - and it is believed that such, "Broad-Based, GENERAL SOLUTIONS" provide HIGHER VALUE - than most all (single-vendor) incarnations.

    Should this vendor "stumble across" this thread - it would be useful if they'd comment upon, "The presence of different and/or extended MCU HW resources" - imposed upon pin "PQ4" only - to enable it to toggle at this much higher frequency.     (FAR exceeds the output capability of ALL OTHER MCU GPIO!)

    One should note that this "PQ4 measurement method" is far more restricted than the use of ANY MCU Timer - and it is, "Unclear if such high frequency - PQ4 output - may be sustained w/out "ill-effects!"  (Being suffered by that pin - or (even worse) - the MCU itself!"     Such "Full Speed Ahead" output surely raises MCU power consumption - and (other) "icebergs" - may be lurking! ... Note that HMS Titanic, "encountered its (unwanted) "sub-surface destiny" - while (also) @ "unguarded, Full Speed"...)  

  • 0 in reply to Chee Chein Wong
    Genius 3850 points
    Use a large enough divider so it doesn't hit the 60Mhz limit. If you observe 20Mhz divsclk at 6x of divider, you know the system clock is 120Mhz.

    For your purpose, you don't need to run divsclk at 1x divider.
  • 0 in reply to Chee Chein Wong
    TI__Guru*** 128155 points

    Hello Chee Chein and cb1,

    I can see further clarity is needed on this topic, hopefully the following comments will help with that.

    1) The GPIO design limits the output to 60MHz as it is not tolerant beyond 60MHz. If you want to confirm that it is running at 120MHz, try out different dividers and you'll see it easily enough. But to be clear, it isn't a divide by 2 circuit otherwise all outputs would be divided.

    Do note that the PQ4 pin outputs the DIVSCLK signal, not System Clock, and the DIVSCLK is not synchronized to system clock. It is meant to be used as a clock source for other devices, and it has no timing relationships to other signals in the device.

    2) I suggested cb1's post as answer as I feel his suggestion of using the timer/PWM method has advantages over DIVSCLK due to the aforementioned synchronization aspect for measuring that the System Clock is running at the desired frequency.

    3) Regarding cb1's question - I am not well versed in exactly how the GPIO for PQ4 is architected, but I feel safe stating that the reason it functions as it does is because it tied into the DIVSCLK output so no peripheral aspects and no CPU processing is needed to output the signal. It's just a raw clock signal with a simple divider between the clock and GPIO, unlike PWM and other peripherals which are configured with more settings and have more overhead.

  • 0 in reply to Ralph Jacobi
    Guru 117850 points

    Thank you Ralph - much appreciated.

    May it be noted that the "just arrived posting" appears in (some) conflict:

    • "it isn't a divide by 2 circuit"

    yet later

    • " just a raw clock signal with a simple divider between the clock and GPIO"

    I believe that (some) case may be made for a "simple divider" being a (near) - or even exact equivalent - of a "divide by two."

    Now as "PQ4" appears only upon the '129 series - it would prove useful if the "hardware treatment" of that specific MCU pin - differs from "normal" GPIO.    One way to discover that may be to compare the scope-cap outputs of PQ4 versus the identical caps from a (different) Timer output pin - operating at its highest PWM frequency.    Should PQ4's hardware be "tweaked" - it is suspected that superior waveforms would result from it - when the frequency matches that of the Timer's PWM output.     If "PQ4" did not receive "special treatment" - the MCU would have added flexibility - if that desirable,  "DIVSCLK output" could be multiplexed upon several candidate MCU pins - and not "confined to PQ4."      It may also prove true that pin "PQ4" is physically closest to "DIVSCLK's" implementation - enabling the shortest internal routing...

    Perhaps of note - once an MCU Timer is configured as "PWM Output" - no futher MCU intervention is required.    (unless some alteration - or cessation - to that output is desired)     The fact that MANY Timers are available - makes their use far more flexible - and (may) make "PQ4's" use questionable - due to its, "Lack of sync. to the System Clock."

    My "stack of chips" (still) rides on PQ4 enjoying "extra output capability" - to (maybe) justify its (many other) limitations...

  • 0 in reply to cb1_mobile
    TI__Guru*** 128155 points
    Hello cb1,

    I'd have to check but I don't think the 4C123 devices have a direct clock output like the 4C129 devices do, which would be the difference. And yes the PWM is free of MCU intervention in the sense of code processing, but I think there is an extra cycle or two required that wouldn't be the case for a pure clock output.

    I think OP's post wasn't that he produced the signal, but that he was trying to do so and failed due to GPIO limits. He states max frequency seen is 60MHz which is as expected.

    And yes, you are right, it is not at all a square wave. Much closer to half of a sine wave than a square wave even on our high end 1GHz sensing scope. Not exactly usable in place of a PWM though it does still clearly define the output frequency. I didn't test where a nice square wave is seen in detail though, so not sure what the 'limit' would be. But since the DIVSCLK output is not synchronous with TM4C Sys Clock, I wouldn't say even with a square wave that it'd be particularly useful beyond sourcing external components.
  • 0 in reply to Ralph Jacobi
    Guru 117850 points
    Hi Ralph,

    Again thanks - I "edited" my response - started prior to yours - (got a foncon) - and completed the post minutes ago.

    Note that my (one up) post seeks to compare the output signal's "purity" "PQ4 vs. any Timer Output - set to same frequency (w/Timer in PWM mode.) I have to believe that "PQ4's output was "beefed up" - otherwise its value is (pardon) slight - even questionable...
  • 0 in reply to cb1_mobile
    TI__Guru*** 128155 points
    Hello cb1,

    I saw your edit this morning but needed to do some leg work before replying as while writing up my reply in attempt to clear up some confusion of my messaging, I decided to test something out.

    So, from my prior post, my understanding was that when I said there is no divider being apply on the output I meant there was no mandatory divider that forcibly forces the frequency output lower. The GPIO is limited to 60MHz, so it won't output 120MHz, but that was not because a *divider* causing that.

    Now after doing some more testing, I have found the exact answer is more complex.

    When the output for the DIVSCLK is set as '0' for the divider which means div by 1, it looks like the GPIO still forces the output to be div by 2, so that would go along with your divider theory from the beginning. I figure this was a design choice made to protect the GPIO from outputting more than 60MHz, as with a divide by 2 minimum on the output, no signal could exceed 60MHz. During my tests, I tested the divider outputs for 40, 60, 80, and 120MHz system clocks with DIVSCLK set for 0 and for 1, and in all cases the settings were aligned in terms of output frequency on the GPIO indicating for the PQ4 output there is no difference between the two settings.

    Though with all that said, the divider then works as advertised for all other settings, dividing as advertised in the datasheet.

    This tells me that there is not a flat divide by 2 on the GPIO in addition to the DIVSCLK settings as other programmed values provide the desired output, but that the simple divider I described being between the raw clock output and the GPIO pin is configured to *at minimum* divide by 2 for the GPIO output, and then it will be map correctly for all other divide settings.

    Hopefully this sheds some more light into the topic.
  • 0 in reply to Ralph Jacobi
    Guru 117850 points

    Ralph,

    Thanks again - appreciated.

    In my "tour @ similar MCU giant" - most always (some) flip-flop was imposed between System Clock and GPIO. (unless that pin was really deemed (very) special. That was my basis - if not done via a "Div by 2 (i.e. FF)" it is unlikely that the cost/size of "bandpass filter" serves to limit frequency. Best we "move on."

    What I believe (still) of value - is "the identification of ANY SPECIAL HW Treatment of "PQ4." (we have NO '129 devices nor boards) Would it not prove "insightful" to compare contrast the output waveforms (even the drive capability) of "PQ4 versus Timer Outputs forced into 50% duty cycle PWM Mode?" Both would be set to the same frequency - and via the attachment of simple resistive load (to either supply rail) - any "Added Output Capability" possessed by PQ4 - could be quickly/easily noted. (recall - you indicated that (some) treatment (appeared) upon PQ4.) If it WAS intended as an output source - "beefing it up" could only help - is that not true? And may prove a Sales Feature - if the implementation (really) offers benefit.

    When you've the time - might you conduct such an experiment? (again - firm/I have No such '129 boards) yet I can identify several opportunities where such an Added Capability WOULD be welcomed...

    Thanks again for your efforts... (past & "hopefully" pending/coming...)

  • 0 in reply to cb1_mobile
    TI__Guru*** 128155 points
    Hello cb1,

    Well, it's purpose is to be an external clock source, not to drive any resistive loads like a PWM, so I have my doubts it would be as successful as the peripheral. But in any case for the foreseeable feature I won't have time to entertain such additional tests just for the sake of teasing out such details of the PQ4 output capability.
  • 0 in reply to Ralph Jacobi
    Guru 117850 points

    That's fair - it should be noted that "Not always" - is a clock-source targeted for "external devices" - confined to "just one!"      Such would not prove "much" - of a clock-source.
    That's the justification for providing "extended drive capability" - especially when "external drive" has been  "represented!"      That "extra drive" may  "avoid" the addition of a buffer - always useful...

    The "resistive load" could be achieved via the temporary attachment of 1/8W resistors.    Expected currents could range between 2 - 20mA - enabling the eased comparison of PQ4 vs. Timer's PWM output - via a variety of GPIO.     (3V3 across 165Ω yields 20mA @ 0.066W)

    In summary - this thread has - without intent - unmasked PQ4's limitations:

    • Not Sync'ed to System Clock  -  that's (more than a little unusual) - and much limits such signal's usefulness
    • Available from "one & only one MCU pin" ... (while Timer pins "burst at the seams" - emerging from ALL sides of the MCU!)

    Thus - PQ4's being of  "improved output capability" - proves its (sole) "saving grace" - does it not?      (otherwise - what IS its point?)

  • 0 in reply to Ralph Jacobi
    Genius 3850 points
    "there is no difference between the two settings."

    that's a fuzzy statement. But sounds like you are saying that setting the system disregarded the divide by 1 settting and treated it as a divide by 2? just for 120Mhz or all frequencies?

    if so, TI should consider amend the datasheet.
  • 0 in reply to Danny F
    TI__Guru*** 128155 points
    Hello Danny,

    Not the system, the GPIO output. Two very different points. The only amendment we'd need to consider is a footnote about the GPIO output specifically regarding to the divider use on the GPIO output when the divide by 1 setting is used - and I say footnote because the datasheet doesn't clearly state what the output at the GPIO would be so it is neither giving wrong information nor painting the full accurate picture. This item has been added to the list.
  • 0 in reply to Ralph Jacobi
    Genius 3850 points
    I thought the datasheet is quite clear about divsclk being a pin, not a signal. the datasheet has divsclk to a pin directly.

    you seem to be saying that (if divsclk is a signal) it will always be correct, ie. the divsclk would be 120Mhz if the DIV field is 0 and the system clock is 120Mhz. It is jus that the GPIO will divide that frequency by 2 if and only if DIV is 0 - your original statement isn't quite clear (to me).

    either way, a clarification would be helpful - only TI understands how the internals work here.
  • 0 in reply to Ralph Jacobi
    Prodigy 230 points
    Hi Ralph,

    Thank you for the verification of the GPIO design limits to output to 60MHz.
  • 0 in reply to Chee Chein Wong
    Guru 117850 points
    You may note that such "tortured/over-stressed" (60MHz) PQ4 output - may not prove of "normal/customary" value...
    A "real" 50% duty cycle Square Wave - may be obtained from ANY of the MCU's Timers - set to PWM & providing (proper) frequency division... Timers prove SO much "more flexible" (and predictable - in terms of I/O) than PQ4...